An integrated variation-aware mapping framework for FinFET based irregular 2D MPSoCs in the dark silicon era
| dc.contributor.author | Rajkrishna, Pramit, author | |
| dc.contributor.author | Pasricha, Sudeep, advisor | |
| dc.contributor.author | Jayasumana, Anura, committee member | |
| dc.contributor.author | Burns, Patrick, committee member | |
| dc.date.accessioned | 2016-07-13T14:50:14Z | |
| dc.date.available | 2016-07-13T14:50:14Z | |
| dc.date.issued | 2016 | |
| dc.description | Zip file contains PowerPoint presentation. | |
| dc.description.abstract | In the deep submicron era, process variations and dark silicon considerations have become prominent focus areas for early stage networks-on-chip (NoC) design synthesis. Additionally, FinFETs have been implemented as promising alternatives to bulk CMOS implementations for 22nm and below technology nodes to mitigate leakage power. While overall system power in a dark silicon paradigm is governed by a limitation on active cores and inter-core communication patterns, it has also become imperative to consider process variations in a holistic context for irregular 2D NoCs. Additionally, manufacturing defects induce link failures, with resultant irregularity in the NoC topology and rendering conventional minimal routing schemes for regular topologies inoperable. In this thesis, we propose a holistic process variation aware design time synthesis framework (HERMES) that performs computation and communication mapping while minimizing energy consumption and maximizing Power Performance Yield (PPY). The framework targets a 22nm FinFET based homogenous NoC implementation with design time link failures in the NoC fabric, a dark silicon based power constraint and system bandwidth constraints for performance guarantees, while preserving connectivity and deadlock freedom in the NoC fabric. Our experimental results show that HERMES performs 1.32x better in energy, 1.29x better in simulation execution time and 58.44% better in PPY statistics, over other state-of-the-art proposed mapping techniques for various SPLASH2 and PARSEC parallel benchmarks. | |
| dc.format.medium | born digital | |
| dc.format.medium | masters theses | |
| dc.format.medium | ZIP | |
| dc.format.medium | PPTX | |
| dc.identifier | Rajkrishna_colostate_0053N_13448.pdf | |
| dc.identifier.uri | http://hdl.handle.net/10217/173465 | |
| dc.language | English | |
| dc.language.iso | eng | |
| dc.publisher | Colorado State University. Libraries | |
| dc.relation.ispartof | 2000-2019 | |
| dc.rights | Copyright and other restrictions may apply. User is responsible for compliance with all applicable laws. For information about copyright law, please see https://libguides.colostate.edu/copyright. | |
| dc.subject | FinFETs | |
| dc.subject | networks on chip | |
| dc.subject | genetic algorithm | |
| dc.subject | dark silicon | |
| dc.title | An integrated variation-aware mapping framework for FinFET based irregular 2D MPSoCs in the dark silicon era | |
| dc.type | Text | |
| dcterms.rights.dpla | This Item is protected by copyright and/or related rights (https://rightsstatements.org/vocab/InC/1.0/). You are free to use this Item in any way that is permitted by the copyright and related rights legislation that applies to your use. For other uses you need to obtain permission from the rights-holder(s). | |
| thesis.degree.discipline | Electrical and Computer Engineering | |
| thesis.degree.grantor | Colorado State University | |
| thesis.degree.level | Masters | |
| thesis.degree.name | Master of Science (M.S.) |