Fabrication and characterization of VCSEL based smart pixels

Abstract

Vertical-cavity surface-emitting laser (VCSEL)-based smart pixel arrays are very well suited for parallel optoelectronic processing and board-to-board interconnection. The integration of VCSELs with foundry fabricated integrated circuits is the key technology required to fabricate the smart pixels needed for these applications. In the research of this dissertation, three hybrid integration techniques for bonding VCSELs to foundry fabricated microelectronic integrated circuit chips have been developed, characterized and compared. Each of the three bonding techniques used different ways of attaching the VCSEL to the integrated circuits and making electrical contacts. All three techniques remove the substrate from the VCSEL wafer leaving an array of individual VCSELs bonded to individual pixels. This dissertation presents the successfully bonding of 8x8 and/or 4x4 VCSEL arrays to CMOS, MESFET and GaAs dummy chips using these three different bonding techniques. The electrical, optical and thermal characteristics of the bonded VCSEL arrays were measured in order to evaluate these bonding techniques. The functionality of the smart pixels with bonded VCSELs was also demonstrated. The measured threshold voltage of the bonded VCSEL is as low as 1.5V and the series resistance is as low as 60Ω, indicating good electrical contacts. Optical power of 3mW for a VCSEL with a 14μm oxide-confined aperture was also observed indicating good thermal contact. The VCSELs were operated at 200Mb/s (our equipment limit) with the rise and fall times of the optical output being<1nS. The thermal resistance of the VCSELs bonded to a GaAs substrate was found to be as low as 1100K/W, indicating a high quality contact. Less than 100K/W thermal crosstalk was also observed in the VCSEL arrays with a 250μm pitch. A two-dimensional thermal transfer model was constructed to analyze the heat transfer of the bonded VCSELs. The model predicted a rapid increase of thermal resistance when the size of the solder bonding pads is less than 10μm. The simulation also verified that the thermal resistance of the VCSEL bonded to a CMOS chip could be reduced by adding vias through the dielectric layers of the CMOS chip or increasing the thickness of the top gold traces.