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Bayesian based stopping rules for behavioral VHDL verification

dc.contributor.authorHajjar, Amjad Fuad A., author
dc.contributor.authorChen, Tom, advisor
dc.contributor.authorAndrews, Anneliese A., committee member
dc.contributor.authorAnderson, Charles W., committee member
dc.contributor.authorWilmsen, Carl, committee member
dc.date.accessioned2026-05-07T18:07:48Z
dc.date.issued2001
dc.description.abstractVerification of complex behavioral models has become a critical and time-consuming process in hardware design. During behavioral model verification, it is important to determine the stopping point for the current test strategy and for moving to a different test strategy. It has been shown that the location of the stopping point is highly dependent on the statistical model one chooses to describe the coverage behavior during the verification process. This research presents Bayesian based statistical stopping rules for behavioral VHDL model verification. Unlike other existing approaches, the statistical assumptions of the proposed stopping rules are based on experimental evaluation of probability distribution functions and correlation functions extracted from simulation results of a suite of HDL models. The resulting assumptions are then employed with proper testing criteria in developing the proposed stopping rules. Fourteen behavioral VHDL models were experimented with to determine the efficiency of the proposed stopping rules over the existing stopping rules. Two metrics for measuring efficiency have been developed to objectively compare between different stopping rules. Results show that the efficiency of using the proposed stopping rules are up to 3 times better than that of using the best existing stopping rule and up to two orders of magnitude better than that without using stopping rules. We also propose a statistical forecasting model that predicts the future coverage during the verification process. The proposed model has high prediction accuracies in determining the probability of having coverage in the future as well as the expected waiting time to a new coverage item within the same prediction window. The estimated prediction error of having coverage was found to be 2% in the worst case when predicting the next 1000 simulation cycles. When extending the prediction window size to 10,000 simulation cycles, the maximum expected errors in predicting the interruption probability is 13%. We believe that the proposed stopping rules and the statistical forecasting model will transform the existing brute-force approaches in behavioral model verification to more intelligent and statistical approaches to meet the tight time-to-market requirement of complex electronic systems without sacrificing the quality of the design.
dc.format.mediumdoctoral dissertations
dc.identifier.urihttps://hdl.handle.net/10217/244395
dc.identifier.urihttps://doi.org/10.25675/3.026990
dc.languageEnglish
dc.language.isoeng
dc.publisherColorado State University. Libraries
dc.relation.ispartof2000-2019
dc.rightsCopyright and other restrictions may apply. User is responsible for compliance with all applicable laws. For information about copyright law, please see https://libguides.colostate.edu/copyright.
dc.rights.licensePer the terms of a contractual agreement, all use of this item is limited to the non-commercial use of Colorado State University and its authorized users.
dc.subjectelectrical engineering
dc.titleBayesian based stopping rules for behavioral VHDL verification
dc.typeText
dcterms.rights.dplaThis Item is protected by copyright and/or related rights (https://rightsstatements.org/vocab/InC/1.0/). You are free to use this Item in any way that is permitted by the copyright and related rights legislation that applies to your use. For other uses you need to obtain permission from the rights-holder(s).
thesis.degree.disciplineElectrical and Computer Engineering
thesis.degree.grantorColorado State University
thesis.degree.levelDoctoral
thesis.degree.nameDoctor of Philosophy (Ph.D.)

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