Design of integrated on-chip impedance sensors
| dc.contributor.author | Kern, Tucker, author | |
| dc.contributor.author | Chen, Thomas W., advisor | |
| dc.contributor.author | Pezeshki, Ali, committee member | |
| dc.contributor.author | Tobet, Stuart, committee member | |
| dc.date.accessioned | 2007-01-03T06:39:32Z | |
| dc.date.available | 2007-01-03T06:39:32Z | |
| dc.date.issued | 2014 | |
| dc.description.abstract | In this thesis two integrated sensor systems for measuring the impedance of a device under test (DUT) are presented. Both sensors have potential applications in label-free affinity biosensors for biological and bio-medical analysis. The first sensor is a purely capacitive sensor that operates on the theory of capacitive division. Test capacitance is placed within a capacitive divider and produces an output voltage proportional to its value. This voltage is then converted to a timedomain signal for easy readout. The prototype capacitive sensor shows a resolution of 5 fF on a base of 500 fF, which corresponds to a 1 % resolution. The second sensor, a general purpose impedance sensor calculates the ratio between a DUT and reference impedance when stimulated by a sinusoidal signal. Computation of DUT magnitude and phase is accomplished in silicon via mixed-signal division and a phase module. An automatic gain controller (AGC) allows the sensor to measure impedance from 30 Ω to 2.5 MΩ with no more than 10 % error and a resolution of at least .44 %. Prototypes of both sensing topologies were implemented in a .18 μm CMOS process and their operation in silicon was verified. The prototype capacitive sensor required a circuit area of .014 mm2 and successfully demonstrated a resolution of 5 fF in silicon. A prototype impedance sensor without the phase module or AGC was implemented with a circuit area of .17 mm2. Functional verification of the peak capture systems and mixed-signal divider was accomplished. The complete implementation of the impedance sensor, with phase module and AGC, requires an estimated .28 mm2 of circuit area. | |
| dc.format.medium | born digital | |
| dc.format.medium | masters theses | |
| dc.identifier | Kern_colostate_0053N_12454.pdf | |
| dc.identifier.uri | http://hdl.handle.net/10217/83982 | |
| dc.language | English | |
| dc.language.iso | eng | |
| dc.publisher | Colorado State University. Libraries | |
| dc.relation.ispartof | 2000-2019 | |
| dc.rights | Copyright and other restrictions may apply. User is responsible for compliance with all applicable laws. For information about copyright law, please see https://libguides.colostate.edu/copyright. | |
| dc.subject | CMOS | |
| dc.subject | sensor | |
| dc.subject | impedance | |
| dc.title | Design of integrated on-chip impedance sensors | |
| dc.type | Text | |
| dcterms.rights.dpla | This Item is protected by copyright and/or related rights (https://rightsstatements.org/vocab/InC/1.0/). You are free to use this Item in any way that is permitted by the copyright and related rights legislation that applies to your use. For other uses you need to obtain permission from the rights-holder(s). | |
| thesis.degree.discipline | Electrical and Computer Engineering | |
| thesis.degree.grantor | Colorado State University | |
| thesis.degree.level | Masters | |
| thesis.degree.name | Master of Science (M.S.) |
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