Hardware implementation and design space exploration for Wave 2D and Jacobi 2D stencil computations
| dc.contributor.author | Chandramohan, Rajbharath, author | |
| dc.contributor.author | Rajopadhye, Sanjay, advisor | |
| dc.contributor.author | Pinaud, Oliver, committee member | |
| dc.contributor.author | Pasricha, Sudeep, committee member | |
| dc.date.accessioned | 2017-06-09T15:41:09Z | |
| dc.date.available | 2017-06-09T15:41:09Z | |
| dc.date.issued | 2017 | |
| dc.description.abstract | Hardware accelerators are highly optimized functional blocks designed to perform specific tasks from the CPU at a higher performance. We developed a hardware accelerator for Jacobi 2D and Wave 2D algorithms, two computations with a stencil pattern. They are used in a lot of scientific applications in the field of acoustics, electro magnetics and Fluid dynamics. These problems have large problem sizes, memory limitations and bandwidth constraints that result in long run times on large problems. Hence, an approach which increases the performance of these problems that reduces bandwidth requirement is necessary. We developed analytical models depicting the performance, Bandwidth and Area models for the Wave 2D algorithm and Jacobi 2D algorithm and solved them for the optimal solution using posynomials and positivity property in MATLAB and using Excel Solver. We split the computation into two levels of tiling. The first level called passes is a rectangular prism that runs through the 3-D iteration space. Each pass is mapped to a grid of processing elements(PEs) in the hardware accelerator. The second level of tiling splits the vertical prism into smaller prisms executed by a single PE. These optimizations are implemented in Verilog using Altera Quartus and simulated using ModelSIM. Results from ModelSIM provides an accurate model and an experimental verification of the design. We also achieved improved performance and lower bandwidth. | |
| dc.format.medium | born digital | |
| dc.format.medium | masters theses | |
| dc.identifier | Chandramohan_colostate_0053N_14078.pdf | |
| dc.identifier.uri | http://hdl.handle.net/10217/181355 | |
| dc.language | English | |
| dc.language.iso | eng | |
| dc.publisher | Colorado State University. Libraries | |
| dc.relation.ispartof | 2000-2019 | |
| dc.rights | Copyright and other restrictions may apply. User is responsible for compliance with all applicable laws. For information about copyright law, please see https://libguides.colostate.edu/copyright. | |
| dc.subject | Jacobi 2D | |
| dc.subject | stencil | |
| dc.subject | hardware accelerator | |
| dc.subject | Wave 2D | |
| dc.subject | optimization | |
| dc.title | Hardware implementation and design space exploration for Wave 2D and Jacobi 2D stencil computations | |
| dc.type | Text | |
| dcterms.rights.dpla | This Item is protected by copyright and/or related rights (https://rightsstatements.org/vocab/InC/1.0/). You are free to use this Item in any way that is permitted by the copyright and related rights legislation that applies to your use. For other uses you need to obtain permission from the rights-holder(s). | |
| thesis.degree.discipline | Electrical and Computer Engineering | |
| thesis.degree.grantor | Colorado State University | |
| thesis.degree.level | Masters | |
| thesis.degree.name | Master of Science (M.S.) |
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