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Hardware implementation and design space exploration for Wave 2D and Jacobi 2D stencil computations




Chandramohan, Rajbharath, author
Rajopadhye, Sanjay, advisor
Pinaud, Oliver, committee member
Pasricha, Sudeep, committee member

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Hardware accelerators are highly optimized functional blocks designed to perform specific tasks from the CPU at a higher performance. We developed a hardware accelerator for Jacobi 2D and Wave 2D algorithms, two computations with a stencil pattern. They are used in a lot of scientific applications in the field of acoustics, electro magnetics and Fluid dynamics. These problems have large problem sizes, memory limitations and bandwidth constraints that result in long run times on large problems. Hence, an approach which increases the performance of these problems that reduces bandwidth requirement is necessary. We developed analytical models depicting the performance, Bandwidth and Area models for the Wave 2D algorithm and Jacobi 2D algorithm and solved them for the optimal solution using posynomials and positivity property in MATLAB and using Excel Solver. We split the computation into two levels of tiling. The first level called passes is a rectangular prism that runs through the 3-D iteration space. Each pass is mapped to a grid of processing elements(PEs) in the hardware accelerator. The second level of tiling splits the vertical prism into smaller prisms executed by a single PE. These optimizations are implemented in Verilog using Altera Quartus and simulated using ModelSIM. Results from ModelSIM provides an accurate model and an experimental verification of the design. We also achieved improved performance and lower bandwidth.


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Jacobi 2D
hardware accelerator
Wave 2D


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