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Mixed-precision S/DGEMM using the TF32 and TF64 frameworks on low-precision AI tensor cores

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dc.contributor.authorValero-Lara, Pedro, author
dc.contributor.authorLiu, Frank, autor
dc.contributor.authorVetter, Jeffrey S., author
dc.contributor.authorJorquera, Ian, author
dc.contributor.authorACM, publisher
dc.date.accessioned2024-11-11T19:30:35Z
dc.date.available2024-11-11T19:30:35Z
dc.date.issued2023-11-12
dc.description.abstractUsing NVIDIA graphics processing units (GPUs) equipped with Tensor Cores has enabled the significant acceleration of general matrix multiplication (GEMM) for applications in machine learning (ML) and artificial intelligence (AI) and in high-performance computing (HPC) generally. The use of such power-efficient, specialized accelerators can provide a performance increase between 8× and 20×, albeit with a loss in precision. However, a high level of precision is required in many large scientific and HPC applications, and computing in single or double precision is still necessary for many of these applications to maintain accuracy. Fortunately, mixed-precision methods can be employed to maintain a higher level of numerical precision while also taking advantage of the performance increases from computing with lower-precision AI cores. With this in mind, we extend the state of the art by using NVIDIA's new TF32 framework. This new framework not only burdens some constraints of the previous frameworks, such as costly 32 16-bit castings but also provides an equivalent precision and performance by using a much simpler approach. We also propose a new framework called TF64 that attempts double-precision arithmetic with low-precision Tensor Cores. Although this framework does not exist yet, we validated the correctness of this idea and achieved an equivalent of 64-bit precision on 32-bit hardware.
dc.format.mediumborn digital
dc.format.mediumarticles
dc.identifier.bibliographicCitationPedro Valero-Lara, Frank Liu, and Jeffrey S. Vetter and Ian Jorquera. 2023. Mixed-Precision S/DGEMM Using the TF32 and TF64 Frameworks on Low- Precision AI Tensor Cores. In Workshops of The International Conference on High Performance Computing, Network, Storage, and Analysis (SC-W 2023), November 12–17, 2023, Denver, CO, USA. ACM, New York, NY, USA, 8 pages. https://doi.org/10.1145/3624062.3624084
dc.identifier.doihttps://doi.org/10.1145/3624062.3624084
dc.identifier.urihttps://hdl.handle.net/10217/239514
dc.languageEnglish
dc.language.isoeng
dc.publisherColorado State University. Libraries
dc.relation.ispartofPublications
dc.relation.ispartofACM DL Digital Library
dc.rights©Pedro, Valero-Lara, et al. ACM 2023. This is the author's version of the work. It is posted here for your personal use. Not for redistribution. The definitive Version of Record was published in SC-W 2023, https://dx.doi.org/10.1145/3624062.3624084 .
dc.subjectmixed precision
dc.subjecttensor core
dc.subjectGEMM
dc.subjectGPUs
dc.titleMixed-precision S/DGEMM using the TF32 and TF64 frameworks on low-precision AI tensor cores
dc.typeText

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