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Analytical cost metrics: days of future past

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dc.contributor.authorPrajapati, Nirmal, author
dc.contributor.authorRajopadhye, Sanjay, advisor
dc.contributor.authorBöhm, Wim, committee member
dc.contributor.authorChong, Edwin, committee member
dc.contributor.authorPouchet, Louis-Noël, committee member
dc.date.accessioned2019-09-10T14:36:54Z
dc.date.available2019-09-10T14:36:54Z
dc.date.issued2019
dc.description.abstractFuture exascale high-performance computing (HPC) systems are expected to be increasingly heterogeneous, consisting of several multi-core CPUs and a large number of accelerators, special-purpose hardware that will increase the computing power of the system in a very energy-efficient way. Specialized, energy-efficient accelerators are also an important component in many diverse systems beyond HPC: gaming machines, general purpose workstations, tablets, phones and other media devices. With Moore's law driving the evolution of hardware platforms towards exascale, the dominant performance metric (time efficiency) has now expanded to also incorporate power/energy efficiency. This work builds analytical cost models for cost metrics such as time, energy, memory access, and silicon area. These models are used to predict the performance of applications, for performance tuning, and chip design. The idea is to work with domain specific accelerators where analytical cost models can be accurately used for performance optimization. The performance optimization problems are formulated as mathematical optimization problems. This work explores the analytical cost modeling and mathematical optimization approach in a few ways. For stencil applications and GPU architectures, the analytical cost models are developed for execution time as well as energy. The models are used for performance tuning over existing architectures, and are coupled with silicon area models of GPU architectures to generate highly efficient architecture configurations. For matrix chain products, analytical closed form solutions for off-chip data movement are built and used to minimize the total data movement cost of a minimum op count tree.
dc.format.mediumborn digital
dc.format.mediumdoctoral dissertations
dc.identifierPrajapati_colostate_0053A_15688.pdf
dc.identifier.urihttps://hdl.handle.net/10217/197455
dc.languageEnglish
dc.language.isoeng
dc.publisherColorado State University. Libraries
dc.relation.ispartof2000-2019
dc.rightsCopyright and other restrictions may apply. User is responsible for compliance with all applicable laws. For information about copyright law, please see https://libguides.colostate.edu/copyright.
dc.subjectexecution time model
dc.subjectperformance tuning
dc.subjectstencils
dc.subjectanalytical cost models
dc.subjectsoftware/hardware codesign
dc.subjectmathematical optimization
dc.subjectmatrix chain products
dc.titleAnalytical cost metrics: days of future past
dc.typeText
dcterms.rights.dplaThis Item is protected by copyright and/or related rights (https://rightsstatements.org/vocab/InC/1.0/). You are free to use this Item in any way that is permitted by the copyright and related rights legislation that applies to your use. For other uses you need to obtain permission from the rights-holder(s).
thesis.degree.disciplineComputer Science
thesis.degree.grantorColorado State University
thesis.degree.levelDoctoral
thesis.degree.nameDoctor of Philosophy (Ph.D.)

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