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    Reducing off-chip memory accesses of wavefront parallel programs in Graphics Processing Units

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    http://hdl.handle.net/10217/88551
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    Ranasinghe_colostate_0053N_12785.pdf (477.4Kb)
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    Abstract
    The power wall is one of the major barriers that stands on the way to exascale computing. To break the power wall, overall system power/energy must be reduced, without affecting the performance. We can decrease energy consumption by designing power efficient hardware and/or software. In this thesis, we present a software approach to lower energy consumption of programs targeted for Graphics Processing Units (GPUs). The main idea is to reduce energy consumption by minimizing the amount of off-chip (global) memory accesses. Off-chip memory accesses can be minimized by improving the last level ...
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    Author(s)
    Ranasinghe, Waruna

    Advisor(s)
    Rajopadhye, Sanjay

    Date Issued
    2014
    Format
    born digital; masters theses
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    • 2000-2019 - CSU Theses and Dissertations
    • Theses and Dissertations - Department of Computer Science

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