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dc.contributor.advisorPasricha, Suddep
dc.contributor.authorDesai, Srinivas
dc.contributor.committeememberRajopadhye, Sanjay
dc.contributor.committeememberMalaiya, Yashwant K.
dc.date.accessioned2015-08-27T03:57:11Z
dc.date.available2015-08-27T03:57:11Z
dc.date.issued2015
dc.description2015 Spring.
dc.descriptionIncludes bibliographical references.
dc.description.abstractFuture applications running on chip multiprocessors (CMPs) with tens to hundreds of cores on a chip will require an efficient inter-core communication strategy to achieve high performance. With recent demonstrations of feasibility in fabricating photonic components for on-chip communication, researchers are now focusing on photonic communication based on-chip networks for future CMPs. Photonic interconnects offer several benefits over conventional electrical on-chip interconnects, such as (1) high-bandwidth support by making use of dense wavelength division multiplexing, (2) distance independent power consumption, (3) significantly lower latency, and (4) improved performance-per-watt. Owing to these advantages, photonic interconnects are being considered as worthy alternatives for existing electrical networks. In this thesis, we design and explore a hierarchical electro-photonic network-on-chip (NoC) architecture called NOVA. NOVA aims to optimize several key design metrics such as throughput, latency, energy-delay-product, and power, which determine the overall system performance of a CMP. NOVA has three levels of communication hierarchy. The first level has a broadband-resonator based photonic switch. The second level consists of a low-loss, silicon-nitride arrayed waveguide grating based router. The last level of the hierarchy is made up of photonic ring waveguides. We have modeled and simulated multiple configurations of the proposed architecture with different designs of the photonic switch and several arbitration techniques on the photonic rings. This comprehensive analysis of NOVA allows us to arrive at an optimal configuration of the network for a given set of input applications and CMP platform. Finally, experimental results are strong indicators for considering the proposed architecture, as the improvements achieved were up to 6.1×, 55%, 5×, and 5.9× in terms of throughput, latency, energy-delay-product, and power compared to other state-of-the-art photonic NoC architectures.
dc.format.mediumborn digital
dc.format.mediummasters theses
dc.identifier.urihttp://hdl.handle.net/10217/166959
dc.languageEnglish
dc.publisherColorado State University. Libraries
dc.relation.ispartof2000-2019 - CSU Theses and Dissertations
dc.rightsCopyright of the original work is retained by the author.
dc.titleDesign and analysis of energy-efficient hierarchical electro-photonic network-on-chip architectures
dc.typeText
dcterms.rights.dplaThe copyright and related rights status of this Item has not been evaluated (https://rightsstatements.org/vocab/CNE/1.0/). Please refer to the organization that has made the Item available for more information.
thesis.degree.disciplineElectrical and Computer Engineering
thesis.degree.grantorColorado State University
thesis.degree.levelMasters
thesis.degree.nameMaster of Science (M.S.)


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