Design and analysis of energy-efficient hierarchical electro-photonic network-on-chip architectures
| dc.contributor.author | Desai, Srinivas, author | |
| dc.contributor.author | Pasricha, Suddep, advisor | |
| dc.contributor.author | Rajopadhye, Sanjay, committee member | |
| dc.contributor.author | Malaiya, Yashwant K., committee member | |
| dc.date.accessioned | 2015-08-27T03:57:11Z | |
| dc.date.available | 2015-08-27T03:57:11Z | |
| dc.date.issued | 2015 | |
| dc.description.abstract | Future applications running on chip multiprocessors (CMPs) with tens to hundreds of cores on a chip will require an efficient inter-core communication strategy to achieve high performance. With recent demonstrations of feasibility in fabricating photonic components for on-chip communication, researchers are now focusing on photonic communication based on-chip networks for future CMPs. Photonic interconnects offer several benefits over conventional electrical on-chip interconnects, such as (1) high-bandwidth support by making use of dense wavelength division multiplexing, (2) distance independent power consumption, (3) significantly lower latency, and (4) improved performance-per-watt. Owing to these advantages, photonic interconnects are being considered as worthy alternatives for existing electrical networks. In this thesis, we design and explore a hierarchical electro-photonic network-on-chip (NoC) architecture called NOVA. NOVA aims to optimize several key design metrics such as throughput, latency, energy-delay-product, and power, which determine the overall system performance of a CMP. NOVA has three levels of communication hierarchy. The first level has a broadband-resonator based photonic switch. The second level consists of a low-loss, silicon-nitride arrayed waveguide grating based router. The last level of the hierarchy is made up of photonic ring waveguides. We have modeled and simulated multiple configurations of the proposed architecture with different designs of the photonic switch and several arbitration techniques on the photonic rings. This comprehensive analysis of NOVA allows us to arrive at an optimal configuration of the network for a given set of input applications and CMP platform. Finally, experimental results are strong indicators for considering the proposed architecture, as the improvements achieved were up to 6.1×, 55%, 5×, and 5.9× in terms of throughput, latency, energy-delay-product, and power compared to other state-of-the-art photonic NoC architectures. | |
| dc.format.medium | born digital | |
| dc.format.medium | masters theses | |
| dc.identifier.uri | http://hdl.handle.net/10217/166959 | |
| dc.language | English | |
| dc.language.iso | eng | |
| dc.publisher | Colorado State University. Libraries | |
| dc.relation.ispartof | 2000-2019 | |
| dc.rights | Copyright and other restrictions may apply. User is responsible for compliance with all applicable laws. For information about copyright law, please see https://libguides.colostate.edu/copyright. | |
| dc.title | Design and analysis of energy-efficient hierarchical electro-photonic network-on-chip architectures | |
| dc.type | Text | |
| dcterms.rights.dpla | This Item is protected by copyright and/or related rights (https://rightsstatements.org/vocab/InC/1.0/). You are free to use this Item in any way that is permitted by the copyright and related rights legislation that applies to your use. For other uses you need to obtain permission from the rights-holder(s). | |
| thesis.degree.discipline | Electrical and Computer Engineering | |
| thesis.degree.grantor | Colorado State University | |
| thesis.degree.level | Masters | |
| thesis.degree.name | Master of Science (M.S.) |
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