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    Reliability-aware and energy-efficient system level design for networks-on-chip

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    http://hdl.handle.net/10217/166872
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    Abstract
    With CMOS technology aggressively scaling into the ultra-deep sub-micron (UDSM) regime and application complexity growing rapidly in recent years, processors today are being driven to integrate multiple cores on a chip. Such chip multiprocessor (CMP) architectures offer unprecedented levels of computing performance for highly parallel emerging applications in the era of digital convergence. However, a major challenge facing the designers of these emerging multicore architectures is the increased likelihood of failure due to the rise in transient, permanent, and intermittent faults caused by a ...
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    Author(s)
    Zou, Yong

    Advisor(s)
    Pasricha, Sudeep

    Date Issued
    2015
    Format
    born digital; doctoral dissertations
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    • 2000-2019 - CSU Theses and Dissertations
    • Theses and Dissertations - Department of Electrical and Computer Engineering

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