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High performance and energy efficient shared hybrid last level cache architecture in multicore systems

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dc.contributor.authorBhosale, Swapnil, author
dc.contributor.authorPasricha, Sudeep, advisor
dc.contributor.authorRoy, Sourajeet, committee member
dc.contributor.authorBohm, Wim, committee member
dc.date.accessioned2019-01-07T17:19:34Z
dc.date.available2019-01-07T17:19:34Z
dc.date.issued2018
dc.description.abstractAs the performance gap between CPU and main memory continues to increase, it causes a significant roadblock to exascale computing. Memory performance has not kept up with CPU performance, and is becoming a bottleneck today, particularly due to the advent of data-intensive applications. To accommodate the vast amount of data required by these applications, emerging non-volatile memory technology STTRAM (Spin-Transfer Torque Random Access Memory) is a good candidate to replace or augment SRAM from last-level cache (LLC) memory because of its high capacity, good scalability, and low power consumption. However, its expensive write operations prevent it from becoming a universal memory candidate. In this thesis, we propose an SRAM-STTRAM hybrid last level cache (LLC) architecture that consumes less energy and performs better than SRAM-only and STTRAM-only LLC. We design an algorithm to reduce write operations to the STTRAM region of the hybrid LLC and consequently minimize the write energy of STTRAM. Compared to two prior state-of-the-art techniques, our proposed technique achieves 29.23% and 5.94% total LLC energy savings and 6.863% and 0.407% performance improvement for various SPLASH2 and PARSEC parallel benchmarks.
dc.format.mediumborn digital
dc.format.mediummasters theses
dc.identifierBhosale_colostate_0053N_15214.pdf
dc.identifier.urihttps://hdl.handle.net/10217/193178
dc.languageEnglish
dc.language.isoeng
dc.publisherColorado State University. Libraries
dc.relation.ispartof2000-2019
dc.rightsCopyright and other restrictions may apply. User is responsible for compliance with all applicable laws. For information about copyright law, please see https://libguides.colostate.edu/copyright.
dc.subjectlast level cache
dc.subjectnon-volatile memory
dc.subjectSTTRAM
dc.subjectLLC energy
dc.subjectcache coherency
dc.subjectperformance
dc.titleHigh performance and energy efficient shared hybrid last level cache architecture in multicore systems
dc.typeText
dcterms.rights.dplaThis Item is protected by copyright and/or related rights (https://rightsstatements.org/vocab/InC/1.0/). You are free to use this Item in any way that is permitted by the copyright and related rights legislation that applies to your use. For other uses you need to obtain permission from the rights-holder(s).
thesis.degree.disciplineElectrical and Computer Engineering
thesis.degree.grantorColorado State University
thesis.degree.levelMasters
thesis.degree.nameMaster of Science (M.S.)

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