Pinholes and morphology of CdS films: the effect on the open circuit voltage of CdTe solar cells
Date
2012
Authors
Tashkandi, Mohammed Abdulaziz, author
Sampath, W. S., advisor
James, Susan P., committee member
Sites, James R., committee member
Olsson, Anders, committee member
Journal Title
Journal ISSN
Volume Title
Abstract
Cadmium telluride (CdTe) solar cells are among the many types of solar cells that have the potential to harness solar energy. CdTe has a band gap of ~1.5 eV that very closely matches the spectrum of the sun. In addition, being a thin film solar cell, the entire thickness of the solar device is a few microns and the energy required to manufacture thin film solar cells is much less than some of the more widely used solar cells. Nevertheless, CdTe solar cells lag behind solar cells of similar band gap materials in open circuit voltage. This voltage deficit can be attributed to many factors among which perfecting the window layer material can be a very important key. The best window layer material in CdTe solar cells was found to be cadmium sulfide (CdS). Usually thick CdS layers on the order of 125nm are used to ensure that the voltage of the solar device is as high as possible, this thickness causes some photons to be absorbed in the window layer and thus reduce the photocurrent output of the solar device and consequently its efficiency. The remedy is then to deposit thin CdS layers, as a result, the photocurrent is increased but the open circuit voltage of the device (VOC) tends to decrease especially when the thickness of the deposited CdS film is less than 80nm. The reduction of VOC as the CdS thickness is reduced may be attributed to discontinuities and defects in the window layer material. Such defects and discontinuities that go through the entire thickness of the CdS film expose the underlying Transparent Conductive Oxide (TCO) surface and thus allow the formation of weak CdTe/TCO diodes that are known to reduce the voltage output of the device. These defects and discontinuities are otherwise known as pinholes. Pinholes can be either of natural or artificial origin. Natural sources of pinholes include CdS grain coalescence and TCO surface roughness and artificial sources include scratches, scuffing marks, cleaning residues and dust and particulates in open lab environment. There has been no detailed study that discussed the following: (i) whether these sources of pinholes can be eliminated especially in CdS films deposited via closed space sublimation, (ii) whether these pinholes are actually the reason why CdTe solar cells made with thin CdS layers have less open circuit voltage, and (iii) estimate the size effect of pinholes in CdTe solar cells, i.e., how large an area of the device is affected compared to the size of pinholes. This study focused on studying CdS films of different thicknesses deposited on TEC10 glass substrates cleaned with different cleaning methods. These films were then surveyed for pinholes using Blue-Light Transmission Optical Microscopy for pinhole observation and analysis of the artificial sources of pinholes. The natural sources of pinholes were analyzed and studied via Scanning Electron Microscopy (SEM) and Energy Dispersive X-ray Spectroscopy (EDS). It was possible to determine the size effect of pinholes by combining images obtained from Electroluminescence (EL) as well as Light Beam Induced Current scans (LBIC). In addition, computer models and simulations using PSpice® and MATLAB® allowed further studying the effects of varying the area of pinholes on the open circuit voltage and compare such results to literature as well as identifying possible pinhole area limits via diode voltage profiles. The results indicated that natural sources of pinholes are not major sources of pinholes in CdS films deposited via closed space sublimation. Cleaning residues was found to be the major source of pinholes in these CdS films. Also, cleaning the glass substrates with plasma prior to CdS film deposition is the key to significantly reduce pinholes in CdS films of thicknesses between 50nm and 200nm. Moreover, cleaning the glass substrates within a class 1 mini-environment did not reduce pinholes in CdS films due to the quality of the cleaning process inside such environment. Nevertheless, maintaining cleaned glass substrates in such environment may help reduce pinholes in CdS films deposited on glass substrates cleaned by standard cleaning or plasma cleaning. On the other hand, it was also found out that pinholes could affect an area that is a much as 15 times larger. The PSpice® and the MATLAB® models showed acceptable agreement with literature findings. Finally, diode voltage profile constructed via PSpice® simulations indicated that a total pinhole area corresponding to 0.001% of the total device area has negligible effects in terms of number of diodes being affected in the solar cell and a corresponding VOC loss of about 30mV.
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Subject
open circuit voltage
CdTe solar cells
pinholes
2D PSpice models
CdS films