Hardware compilation of streams and processes

Abstract

A field programmable gate array (FPGA) is a reconfigurable hardware device on which highly parallel algorithms can be executed efficiently. Currently, the task of programming an FPGA is difficult. It involves understanding the hardware characteristics (including timing specifications) as well as understanding the software API issues. The Cameron project has developed a high-level language, called SA-C, for writing image processing application for FPGAs. The goal of this dissertation is to expand the SA-C language capabilities and generalize the target hardware model of the SA-C compiler and make it more efficient. This dissertation investigates issues involved in mapping problem-size independent, space efficient circuits onto the target hardware model. It also expands the SA-C language to introduce non-strict data structures (streams) and concurrent processes. Introduction of concurrent processes not only allows mapping of time-efficient circuits, but also improves the expressibility of the language. This dissertation compares the space versus time efficiency issues involved when parallelizing algorithms. It identifies the conditions when certain parallelizing optimizations (like loop fusion) provide more benefit over concurrent processes.