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Automating the derivation of memory allocations for acceleration of polyhedral programs

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dc.contributor.authorFerry, Corentin, author
dc.contributor.authorRajopadhye, Sanjay, advisor
dc.contributor.authorDerrien, Steven, advisor
dc.contributor.authorWilson, Jesse, committee member
dc.contributor.authorPasricha, Sudeep, committee member
dc.contributor.authorMcClurg, Jedidiah, committee member
dc.contributor.authorSadayappan, Ponnuswamy, committee member
dc.contributor.authorde Dinechin, Florent, committee member
dc.contributor.authorCollange, Caroline, committee member
dc.date.accessioned2024-05-27T10:32:48Z
dc.date.available2024-05-27T10:32:48Z
dc.date.issued2024
dc.description.abstractAs processors compute power keeps increasing, so do their demands in memory accesses: some computations will require a higher bandwidth and exhibit regular memory access patterns, others will require a lower access latency and exhibit random access patterns. To cope with all demands, memory technologies are becoming diverse. It is then necessary to adapt both programs and hardware accelerators to the memory technology they use. Notably, memory access patterns and memory layouts have to be optimized. Manual optimization can be extremely tedious and does not scale to a large number of processors and memories, where automation becomes necessary. In this Ph.D dissertation, we suggest several automated methods to derive data layouts from programs, notably for FPGA accelerators. We focus on getting the best throughput from high-latency, high-bandwidth memories and, for all kinds of memories, the lowest redundancy while preserving contiguity. To this effect, we introduce mathematical analyses to partition the data flow of a program with uniform and affine dependence patterns, propose memory layouts and automation techniques to get optimized FPGA accelerators.
dc.format.mediumborn digital
dc.format.mediumdoctoral dissertations
dc.identifierFerry_colostate_0053A_18231.pdf
dc.identifier.urihttps://hdl.handle.net/10217/238480
dc.languageEnglish
dc.language.isoeng
dc.publisherColorado State University. Libraries
dc.relation.ispartof2020-
dc.rightsCopyright and other restrictions may apply. User is responsible for compliance with all applicable laws. For information about copyright law, please see https://libguides.colostate.edu/copyright.
dc.subjecthigh-level synthesis
dc.subjectpolyhedral model
dc.subjectmemory
dc.subjectcompilers
dc.titleAutomating the derivation of memory allocations for acceleration of polyhedral programs
dc.typeText
dcterms.rights.dplaThis Item is protected by copyright and/or related rights (https://rightsstatements.org/vocab/InC/1.0/). You are free to use this Item in any way that is permitted by the copyright and related rights legislation that applies to your use. For other uses you need to obtain permission from the rights-holder(s).
thesis.degree.disciplineComputer Science
thesis.degree.grantorColorado State University
thesis.degree.levelDoctoral
thesis.degree.nameDoctor of Philosophy (Ph.D.)

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