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Compiling dataflow graphs into hardware

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dc.contributor.authorRinker, Robert E., author
dc.contributor.authorNajjar, Walid, advisor
dc.contributor.authorBöhm, Wim, committee member
dc.contributor.authorGrit, Dale H., committee member
dc.contributor.authorJayasumana, Anura P., committee member
dc.date.accessioned2007-01-03T04:43:07Z
dc.date.available2007-01-03T04:43:07Z
dc.date.issued2005
dc.descriptionDepartment Head: L. Darrell Whitley.
dc.description.abstractConventional computers are programmed by supplying a sequence of instructions that perform the desired task. A reconfigurable processor is "programmed" by specifying the interconnections between hardware components, thereby creating a "hardwired" system to do the particular task. For some applications such as image processing, reconfigurable processors can produce dramatic execution speedups. However, programming a reconfigurable processor is essentially a hardware design discipline, making programming difficult for application programmers who are only familiar with software design techniques. To bridge this gap, a programming language, called SA-C (Single Assignment C, pronounced "sassy"), has been designed for programming reconfigurable processors. The process involves two main steps - first, the SA-C compiler analyzes the input source code and produces a hardware-independent intermediate representation of the program, called a dataflow graph (DFG). Secondly, this DFG is combined with hardware-specific information to create the final configuration. This dissertation describes the design and implementation of a system that performs the DFG to hardware translation. The DFG is broken up into three sections: the data generators, the inner loop body, and the data collectors. The second of these, the inner loop body, is used to create a computational structure that is unique for each program. The other two sections are implemented by using prebuilt modules, parameterized for the particular problem. Finally, a "glue module" is created to connect the various pieces into a complete interconnection specification. The dissertation also explores optimizations that can be applied while processing the DFG, to improve performance. A technique for pipelining the inner loop body is described that uses an estimation tool for the propagation delay of the nodes within the dataflow graph. A scheme is also described that identifies subgraphs with the dataflow graph that can be replaced with lookup tables. The lookup tables provide a faster implementation than random logic in some instances.
dc.format.mediumdoctoral dissertations
dc.identifier2005_fall_Rinker_COMS.pdf
dc.identifierETDF2005100001COMS
dc.identifier.urihttp://hdl.handle.net/10217/26316
dc.languageEnglish
dc.language.isoeng
dc.publisherColorado State University. Libraries
dc.relationCatalog record number (MMS ID): 991022400499703361
dc.relationQA76.76.C65.R455 2005
dc.relation.ispartof2000-2019
dc.rightsCopyright and other restrictions may apply. User is responsible for compliance with all applicable laws. For information about copyright law, please see https://libguides.colostate.edu/copyright.
dc.titleCompiling dataflow graphs into hardware
dc.typeText
dcterms.rights.dplaThis Item is protected by copyright and/or related rights (https://rightsstatements.org/vocab/InC/1.0/). You are free to use this Item in any way that is permitted by the copyright and related rights legislation that applies to your use. For other uses you need to obtain permission from the rights-holder(s).
thesis.degree.disciplineComputer Science
thesis.degree.grantorColorado State University
thesis.degree.levelDoctoral
thesis.degree.nameDoctor of Philosophy (Ph.D.)

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