Sensitivity analysis of critical parameters in board test
| dc.contributor.author | Tegethoff, Mick M. V., author | |
| dc.contributor.author | Chen, Tom W., author | |
| dc.contributor.author | IEEE, publisher | |
| dc.date.accessioned | 2007-01-03T06:15:58Z | |
| dc.date.available | 2007-01-03T06:15:58Z | |
| dc.date.issued | 1996 | |
| dc.description.abstract | The authors analyze the main contributors to the quality and cost of complex boards. With manufacturing data from Hewlett-Packard boards, they use simulation models to derive the sensitivity of quality and cost to the solder defect rate, the functional defect rate, and test coverage. They also give a simple cost estimate of implementing IEEE 1149.1 boundary scan on ASICs. Their new yield model, which accounts for solder defect clustering, provides highly accurate yield predictions. | |
| dc.format.medium | born digital | |
| dc.format.medium | articles | |
| dc.identifier.bibliographicCitation | Tegethoff, Mick M. V. and Tom W. Chen, Sensitivity Analysis of Critical Parameters in Board Test, IEEE Design & Test of Computers 13, no. 1 (Spring 1996): 58-63. | |
| dc.identifier.uri | http://hdl.handle.net/10217/1204 | |
| dc.language | English | |
| dc.language.iso | eng | |
| dc.publisher | Colorado State University. Libraries | |
| dc.relation.ispartof | Faculty Publications | |
| dc.rights | ©1996 IEEE. | |
| dc.rights | Copyright and other restrictions may apply. User is responsible for compliance with all applicable laws. For information about copyright law, please see https://libguides.colostate.edu/copyright. | |
| dc.subject | sensitivity analysis | |
| dc.subject | printed circuits | |
| dc.subject | CAD | |
| dc.subject | printed circuit testing | |
| dc.title | Sensitivity analysis of critical parameters in board test | |
| dc.type | Text |
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