Design, characterization, and optimization of photonic neural processors and memories

Abstract

Silicon photonic integrated circuits (PICs) have emerged as a solution to address the escalating demand for high-speed data transmission in next-generation applications. These circuits offer substantial advantages over traditional electronic circuits, such as reduced power consumption, minimal heat dissipation, and the ability to support ultra-high data bandwidths. As the progress of Moore's Law has decelerated and Dennard scaling has reached its limits, silicon photonics presents a viable path forward for enhancing data movement and computational performance in future computing architectures. In silicon-based PICs, optical signals are manipulated and routed using optical waveguides, which are structures that guide light along predetermined paths. The speed and energy efficiency of photonic components have motivated researchers to also exploit silicon photonics for high-performance computing and optical processing. For example, it is possible to use photonic components to perform matrix–vector multiplication, the most computationally intensive operation in deep neural networks, and doing so can reduce computation time in such networks from O(N2) to O(1) by taking advantage of the natural parallelism of optics. Traditionally, these operations have relied on bulky optical components, but the continuous advancement of silicon photonics has enabled small-footprint, low-latency, and energy-efficient optical domain data processing. As a result, by communicating, detecting, and processing information directly in the optical domain, silicon photonic nanoprocessors will have the potential to provide very high footprint and energy efficiencies. More recently, the integration of silicon photonic devices and phase change materials (PCMs) has created a unique opportunity to realize adaptable, reconfigurable, and programmable photonic platforms. In particular, the nonvolatile programmability in phase change materials has made them a promising candidate for implementing photonic memory cells and architectures. Accordingly, photonic memory systems and even in-memory photonic computing paradigms are on the rise, especially given their potential for improving data access in electronic and photonic processors. However, there are still many challenges in the design and fabrication of phase-change photonic integrated circuits, which need to be addressed. This PhD thesis addresses two major areas in the design, characterization, and optimization of photonic processors and memories. First, we explore the fundamentals of phase-change materials (PCMs) and how their behavior can be modeled when integrated with silicon photonic devices to implement reconfigurable photonic components. These components can be tuned to suit various applications. Leveraging the unique non-volatile optical properties of PCMs, we propose a design-space exploration for their co-integration with silicon photonics to realize photonic memory devices with zero static power consumption. This is crucial for eliminating the need for electrical-to-optical (E-O) and optical-to-electrical (O-E) conversions for weight readout when being used in optical computing systems, paving the way toward a fully optical and energy-efficient computing ecosystem. We propose a bottom-up framework to design a novel photonic linear multiplier using tunable directional couplers (DCs) integrated with PCMs. To address the slow response and high-power consumption of the PCM-based photonic devices, including photonic memories, we characterize a new type of PCM with birefringence properties. Such a material shows anisotropic optical properties and can change the group delay and polarisation of interacting polarized electromagnetic waves. Starting from this, we propose polarisation encodable photonic memories and photonic computing units using 2D ferroelectric material whose phase change can happen in the order of nanoseconds, which is aligned with the phonon dispersion relation. Second, we propose a novel fully programmable linear photonic processor, which we call LightPro, with improved scalability, performance, and footprint. At the heart of LightPro are compact, low-loss, and programmable SiPh directional coupler (DC) devices that deploy phase-change material (PCM) for programming the DC's splitting ratio. By thermally inducing phase transitions in the PCM, the coupling coefficient of the DC can be dynamically adjusted to achieve different splitting ratios in the device output. Building on this device foundation, we develop a neural architecture search (NAS) and pruning algorithm to optimize the architecture of the processor for performing MVM operations. Additionally, we address the challenges in designing coherent photonic multipliers that rely on single-frequency operation and optical interference through cascaded networks of Mach-Zehnder Interferometers (MZIs). Specifically, we model the accumulated effects of optical loss, crosstalk, and fabrication process variations (FPVs) in silicon photonic devices—particularly in MZIs—and analyze how these imperfections impact system-level performance when scaled to implement coherent silicon photonic neural networks. Our findings indicate that network accuracy can degrade by up to 85% due to the cumulative effects of optical loss, crosstalk, and phase noise resulting from FPVs. To address these limitations, we propose robust and optimized silicon photonic device designs that can partially mitigate such issues at the design stage.