AGING-INDUCED DATA IMPRINTING IN SRAM ARRAYS: CHARACTERIZATION, ANALYSIS, AND MITIGATION

Abstract

Static random-access memory (SRAM) power-up states are widely used as a source of randomnessand device uniqueness, but they can also retain traces of previously stored information after prolonged stress, creating an end-of-life security vulnerability. This thesis investigates both the formation of aging-induced data imprinting in commercial off-the-shelf (COTS) SRAMs and the mitigation of such imprints through radiation-based sanitization. Under accelerated thermal aging, multiple SRAM chips from different vendors and technology nodes exhibit reverse imprinting, in which the post-aging power-up state becomes biased toward the complement of the stored data pattern. The imprint strength depends on aging temperature, stress duration, and supply voltage, while relaxation measurements show that the induced patterns can remain visible for months at room temperature. The observed behavior indicates that negative bias temperature instability (NBTI)-induced threshold-voltage shifts in PMOS transistors are the dominant mechanism responsible for the effect. To mitigate this vulnerability, this thesis further demonstrates a total ionizing dose (TID)-based sanitization technique for aged SRAM arrays. Experimental results show near-complete sanitization at approximately 50-100 krad(Si) for most of the aged chips. Overall, this thesis highlights both the security risk posed by aging-induced SRAM data imprinting and the effectiveness of radiation-based sanitization as a practical end-of-life mitigation approach.