Characterization of cadmium telluride grain boundaries in cadmium telluride/cadmium sulfide solar cells

Abstract

The in-plane electrical properties of polycrystalline CdTe have been evaluated at various stages in the processing of CdTe/CdS solar cells. This was made feasible by a new lift-off technique, which separates the CdTe layer. In addition, the theory for electrical conduction across grain-boundaries has been extended in that an analytical solution was developed for both one-step and two-step, thermally-assisted tunneling mechanisms. When compared to other conduction mechanisms, it was found that the thermally-assisted tunneling conduction mechanisms gave the best fits to in-plane current versus temperature data for most of the lift-off CdTe samples herein. Values for the grain-boundary barrier height, the barrier height inhomogeneity, and the doping within the vicinity of the grain boundary were determined from the fits. The CdCl2 treatment was found to increase the hole grain-boundary barrier height by about 37%, and the doping in the vicinity of the grain boundary was found to increase by about 0.5 - 1 order of magnitude. Also shown was a non-uniform doping level in the grains all samples, with the doping near the grain boundary several orders of magnitude higher than the bulk concentration. The bulk concentration was determined from a high-frequency, in-plane impedance measurement. This information has allowed a detailed development of the grain-boundary band diagram, which predicts an electron, or minority-carrier barrier due to the variable p-type doping. This barrier may act to reflect the minority carriers before the grain boundary, and reduce minority-carrier recombination. It was also shown that the Nitric-Phosphoric (NP) etching reduces the grain-boundary barrier heights to a value that correlates with the valence-band offsets between CdTe and Te. This effect of the NP-etch on grain boundaries extends down a minimum of 2.5 μm from the etched back contact surface. The effects of the NP-etch are also shown to be unstable and could translate to severe increases in the back-contact series resistance of devices. Finally, it was shown that there was no significant effect of the CdTe source plate usage on the in-plane electrical properties, and that there is no indication of any grain-boundary barrier height inhomogeneity in any of the samples.