An abstract target architecture for FPGA compilation

Abstract

Modern field programmable gate arrays (FPGAs) can outperform general purpose processors on a wide variety of tasks. They are particularly well suited for regular computations in which fine-grained parallelism can be exploited. Despite their tremendous potential for speedup, most high-performance application programmers do not use FPGAs because there is currently no widely accepted programming paradigm. Typical FPGA application design is done at a very low level and requires detailed knowledge of the target FPGA resources and hardware design practices in general. The primary goal of this dissertation is to provide a flexible, high-performance framework for programming FPGAs, without requiring the user to be concerned with hardware design details. The Aggregated Hierarchical Abstract Hardware Architecture (AHAHA) presented here is the target architecture used in the SA-C* compiler; however, its concepts can easily be adapted to other compilers which use dataflow graphs as internal structures. It allows developers of high-level language compilers to concentrate on language features, program optimizations, and exploiting parallelism, without being concerned with the specifics of hardware design. By using the AHAHA framework as an intermediate form when targeting FPGAs, more advanced compilers can be developed to unleash the computational potential of FPGAs. The AHAHA embodies several novel ideas which contribute to its success, however, the principal contribution is its handshaking model which is based on "sections". Using the SA-C compiler as an example, the research presented in this dissertation will answer questions regarding the ramifications of using an abstraction of the FPGA hardware. The AHAHA imposes a well-defined structure on the otherwise unconstrained hardware. This formal structure simplifies compiler development, and its impact upon clock frequency and area are negligible. The benefits of using an abstraction of the FPGA far outweigh the penalties. The AHAHA framework imposes no significant restrictions on the types of programs which may be implemented on the FPGA and maximizes efficiency via effective use of the hardware resources.