Rapid early design space exploration using legacy design data, technology scaling trend and in-situ macro models
Date
2009
Journal Title
Journal ISSN
Volume Title
Abstract
CMOS technology scaling trend, i.e. the doubling of the operating frequency and the doubling of the number of transistors on a die every eighteen months, also know as Moore's Law has been a fundamental driver for the semiconductor industry for well over three decades. Scaling CMOS technologies into deep sub micron especially into sub 100 nm dimensions have caused a significant shift in business and design philosophy, and methodology. In addition to the semiconductor industry maturation there are seven key disruptive trends impacting the semiconductor industry. They are competitive landscape changes, technology convergence, greater global connectedness, increased design complexity, commoditization, consumerization, and the soaring research, development and engineering costs. These disruptions have made traditional business models increasingly ineffective and the benefits of Moore's Law insufficient for sustained competitiveness [1]. 'More-than-Moore' approach to heterogeneous system integration and holistic system optimization strategies in addition to the benefits of technology scaling are necessary for future success [2] [3].
Embedded computation systems and microprocessor designs have significantly benefitted from "cramming" more transistor on a single die. When memory is included on die (with large amounts of cache on die) the latency incurred in moving data and instructions to the computation units reduces sharply, increasing the overall instruction execution rate and ultimately increasing performance. Increase in operating frequency being another aspect of technology scaling, improves the number of instruction executed per unit time. In a superscalar execution pipeline, increasing operating frequency increases overall instruction execution rate and throughput. The conventional design flow for computation engines (embedded computation systems and microprocessors) starts with architectural design followed by physical design. In nanometer CMOS technologies, successful physical implementation of a highly optimized architectural design is not guaranteed due to power consumption variations, signal integrity and processing challenges.
Consequently, design convergence in both power and performance have become increasing difficult with increasing levels of system integration, design complexity and technology scaling related uncertainties. As a result, traditional compartmentalized design methodologies are no longer sufficient as they lead to designs that are pessimistic, slow and/or power hungry. A holistic and systematic understanding of the various design tradeoffs and exploring the design solution space extensively early in the design phase improves design convergence. Some design challenges can be best addressed at the circuit level, others are most effectively addressed at the architecture or system level. With increasingly competitive business conditions dictating design cycle times and time-to-market window, a thorough design space exploration at an early stage of a design can put the design in an optimal subspace for better convergence and for avoiding costly redesigns later on in the design cycle. Rapid and effective design space exploration at all stages of a design process enables faster design convergence and meeting time-to-market stipulation. Design space exploration is important and particularly effective during the early stage of a design where design decisions can have a significant impact on design convergence. A holistic approach to system design is possible only when design tools and aids that incorporate high level system models are easily available to perform tradeoff analysis and design space exploration.
This work proposes a system level design framework for early design space exploration with a focus on power and performance tradeoffs using analytical power and performance prediction models. The analytical prediction models are driven by legacy design data, technology scaling trend, low level physical design parameters and in-situ simulations. Experiments on ISCAS benchmark circuits validate the feasibility of the proposed approach and yielded power centric designs that improved power by 7%-32% for a corresponding 0%-9% performance impact; or performance centric designs with improved performance of 11.25%-17% for a corresponding 2%-3.85% power penalty. Evolutionary algorithm based Pareto analysis on an industrial 65 nm design uncovered design tradeoffs which are not obvious to designers and optimize both power and performance. The high performance design option of the industrial design improved the straight-ported design's performance by 29% with a 2.5% power penalty, whereas the low power design option reduced the straight-ported design's power consumption by 40% for a 9% performance penalty.
The design framework and methodology developed and demonstrated in this work form the foundational steps for early design space exploration utilizing technology scaling trends, process dependent parameters and in-situ simulations. Analytical prediction models are currently limited only to predicting power and performance. Prediction models for yield, chip area and system reliability are seen as valuable future additions to EIDAs capability. Modeling the impact of process variation and the ability to incorporate statistical inputs and outputs are seen as an another incremental improvement to EIDAs value as a design tool. In addition to the above improvements, a macromodel based critical path delay calculation technique including clock and signal uncertainties, incorporating special libraries, RF and analog modules in the system model and, improving the evolutionary algorithm used for design space exploration are salient direction for future research.
Embedded computation systems and microprocessor designs have significantly benefitted from "cramming" more transistor on a single die. When memory is included on die (with large amounts of cache on die) the latency incurred in moving data and instructions to the computation units reduces sharply, increasing the overall instruction execution rate and ultimately increasing performance. Increase in operating frequency being another aspect of technology scaling, improves the number of instruction executed per unit time. In a superscalar execution pipeline, increasing operating frequency increases overall instruction execution rate and throughput. The conventional design flow for computation engines (embedded computation systems and microprocessors) starts with architectural design followed by physical design. In nanometer CMOS technologies, successful physical implementation of a highly optimized architectural design is not guaranteed due to power consumption variations, signal integrity and processing challenges.
Consequently, design convergence in both power and performance have become increasing difficult with increasing levels of system integration, design complexity and technology scaling related uncertainties. As a result, traditional compartmentalized design methodologies are no longer sufficient as they lead to designs that are pessimistic, slow and/or power hungry. A holistic and systematic understanding of the various design tradeoffs and exploring the design solution space extensively early in the design phase improves design convergence. Some design challenges can be best addressed at the circuit level, others are most effectively addressed at the architecture or system level. With increasingly competitive business conditions dictating design cycle times and time-to-market window, a thorough design space exploration at an early stage of a design can put the design in an optimal subspace for better convergence and for avoiding costly redesigns later on in the design cycle. Rapid and effective design space exploration at all stages of a design process enables faster design convergence and meeting time-to-market stipulation. Design space exploration is important and particularly effective during the early stage of a design where design decisions can have a significant impact on design convergence. A holistic approach to system design is possible only when design tools and aids that incorporate high level system models are easily available to perform tradeoff analysis and design space exploration.
This work proposes a system level design framework for early design space exploration with a focus on power and performance tradeoffs using analytical power and performance prediction models. The analytical prediction models are driven by legacy design data, technology scaling trend, low level physical design parameters and in-situ simulations. Experiments on ISCAS benchmark circuits validate the feasibility of the proposed approach and yielded power centric designs that improved power by 7%-32% for a corresponding 0%-9% performance impact; or performance centric designs with improved performance of 11.25%-17% for a corresponding 2%-3.85% power penalty. Evolutionary algorithm based Pareto analysis on an industrial 65 nm design uncovered design tradeoffs which are not obvious to designers and optimize both power and performance. The high performance design option of the industrial design improved the straight-ported design's performance by 29% with a 2.5% power penalty, whereas the low power design option reduced the straight-ported design's power consumption by 40% for a 9% performance penalty.
The design framework and methodology developed and demonstrated in this work form the foundational steps for early design space exploration utilizing technology scaling trends, process dependent parameters and in-situ simulations. Analytical prediction models are currently limited only to predicting power and performance. Prediction models for yield, chip area and system reliability are seen as valuable future additions to EIDAs capability. Modeling the impact of process variation and the ability to incorporate statistical inputs and outputs are seen as an another incremental improvement to EIDAs value as a design tool. In addition to the above improvements, a macromodel based critical path delay calculation technique including clock and signal uncertainties, incorporating special libraries, RF and analog modules in the system model and, improving the evolutionary algorithm used for design space exploration are salient direction for future research.
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Subject
design space exploration
performance prediction
power tradeoffs
computer engineering