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dc.contributor.authorEndsley, Neil H.
dc.contributor.authorGabriel, Arthur R.
dc.contributor.authorScharf, Louis L.
dc.contributor.authorBurleson, Wayne P.
dc.date1989
dc.date.accessioned2007-01-03T04:18:33Z
dc.date.available2007-01-03T04:18:33Z
dc.identifier.citationBurleson, Wayne, P., et al., A Systolic VLSI Chip for Implementing Orthogonal Transforms, IEEE Journal of Solid-State Circuits 24, no. 2 (April 1989): 466-469.
dc.identifier.urihttp://hdl.handle.net/10217/735
dc.descriptionIncludes bibliographical references.
dc.description.abstractThis paper describes the design of a systolic VLSI chip for the implementation of signal processing algorithms that may be decomposed into a product of simple real rotations. These include orthogonal transformations. Applications of this chip include projections, discrete Fourier and cosine transforms, and geometrical transformations. Large transforms may be computed by "tiling" together many chips for increased throughput. A CMOS VLSI chip containing 138 000 transistors in a 5x3 array of rotators has been designed, fabricated, and tested. The chip has a 32-MHz clock and performs real rotations at a rate of 30 MHz. The systolic nature of the chip makes use of fully synchronous bit-serial interconnect and a very regular structure at the rotator and bit levels. A distributed arithmetic scheme is used to implement the matrix-vector multiplication of the rotation.
dc.description.sponsorshipThis work was supported by Ball Aerospace, Boulder, CO, and by the Office of Naval Research, Electronics Branch, Arlington, VA, under Contract ONR 85-K-0693
dc.format.extent4 pages
dc.languageEnglish
dc.language.isoeng
dc.publisherColorado State University. Libraries
dc.rights©1989 IEEE
dc.subjectCMOS integrated circuits
dc.subjectVLSI
dc.subjectcellular arrays
dc.subjectcomputerised signal processing
dc.subjectdigital arithmetic
dc.subjectdigital signal processing chips
dc.subjectparallel architectures
dc.subjectpipeline processing
dc.subjectreal-time systems
dc.subjecttransforms
dc.titleA Systolic VLSI chip for implementing orthogonal transforms
dc.typeArticle
dc.publisher.originalIEEE


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