Repository logo

Browsing by Author "Buddhanoy, Matchima, author"

Now showing 1 - 2 of 2
  • Thumbnail Image
    ItemOpen Access
    Improving block management in 3D NAND flash SSDs with sub-block first write sequencing
    (Colorado State University. Libraries, 2024-06-12) Buddhanoy, Matchima, author; Khan, Kamil, author; Milenkovic, Aleksandar, author; Pasricha, Sudeep, author; Ray, Biswajit, author; ACM, publisher
    Continual vertical scaling in 3D NAND flash solid-state drives (SSDs) results in larger memory blocks, causing performance degradation due to big-block management issues. Pages within a 3D NAND flash block are traditionally written using layer first write sequencing. This paper introduces and explores the benefits of an alternative sub-block first write sequence. This method when coupled with sub-block erase operations promises to alleviate the big-block problem. Our evaluation on a commercial 32-layer 3D NAND flash SSD chip shows that though the proposed method increases the raw bit error rate (RBER), it remains below the threshold that can be corrected by error correction codes (ECCs). Simulation analysis further shows that our proposed method reduces garbage collection overhead, resulting in 36.0% lower response time and 9.6% reduction in additional writes due to garbage collection compared to traditional 3D NAND flash SSDs.
  • Thumbnail Image
    ItemOpen Access
    Life-after-death: exploring thermal annealing conditions to enhance 3D NAND SSD endurance
    (Colorado State University. Libraries, 2024-07-08) Buddhanoy, Matchima, author; Pasricha, Sudeep, author; Ray, Biswajit, author; ACM, publisher
    In this paper, we evaluate thermal annealing effects on the endurance of commercial off-the-shelf (COTS) 3D NAND flash memory beyond its end-of-life. We systematically evaluate the effects of anneal duration, anneal temperature, and state of the memory cells during annealing on the endurance enhancement. Interestingly, we find that endurance enhancement critically depends on the state of flash memory cells during annealing, with programmed cells showing significantly larger improvements than erased cells. Our experimental evaluation indicates that the post-cycle data retention property of an annealed chip significantly improves after thermal annealing, resulting in ∼30% endurance recovery. Our results have significant implications for the future wear-leveling algorithms of SSD-based storage systems.