Design strategies for high-efficiency CdTe solar cells - Song, Tao, author; Sites, James R., advisor; Kanevce, Ana, committee member; Gelfand, Martin, committee member; Wu, Mingzhong, committee member; Sampath, W. S., committee member (Colorado State University. Libraries, 2017)
With continuous technology advances over the past years, CdTe solar cells have surged to be a leading contributor in thin-film photovoltaic (PV) field. While empirical material and device optimization has led to considerable progress, further device optimization requires accurate device models that are able to provide an in-depth understanding of CdTe device physics. Consequently, this thesis is intended to develop a comprehensive model system for high-efficiency CdTe devices through applying basic design principles of solar cells with numerical modeling and comparing results with experimental CdTe devices. Four key topics about high-efficiency CdTe cells are covered in this dissertation: (a) material optimization of CdTe absorber, (b) roles of emitter/absorber interface on carrier transport, (c) substrate choices for monocrystalline CdTe cells, and (d) back contact configurations for thin-film polycrystalline CdTe cells. Finally, comparisons between simulation and experiment are carried out to identify both beneficial and detrimental mechanisms for CdTe cell performance and to guide future cell optimization. The CdTe absorber is central to cell performance. Numerical simulation has shown the feasibility of high energy-conversion efficiency (open-circuit voltage VOC > 1000 mV, efficiency η > 25%), which requires both high carrier density (p >1016 cm-3) and long minority carrier lifetime (τn > 100 ns). As the minority carrier lifetime increases (τn > 10 ns), the carrier recombination at the back surface becomes a limitation for cell performance with absorber thickness < 3 µm. Hence, either a thicker absorber or an appropriate back-surface-field layer is a requisite for reducing the back-surface recombination. When integrating layers into devices, more careful design of interfaces is needed. One consideration is the emitter/absorber interface. It is shown that a positive conduction-band offset ΔEC ("spike") at the interface is beneficial to cell performance, since it can induce a large valence-band bending which suppresses the hole injection near the interface for the electron-hole recombination, but too large a spike is detrimental to photocurrent transport. In a heterojunction device with many defects at the emitter/absorber interface (high SIF), a thin and highly-doped emitter can induce strong absorber inversion and hence help maintain good cell performance. Performance losses from acceptor-type interface defects can be significant when interface defect states are located near mid-gap energies. In terms of specific emitter materials, the calculations suggest that the (Mg,Zn)O alloy with 20% Mg, or a similar type-I heterojunction partner with moderate ΔEC (e.g., Cd(S,O) or (Cd,Mg)Te with appropriate oxygen or magnesium ratios) should yield higher voltages and would therefore be better candidates for the CdTe-cell emitter. The CdTe/substrate interface is also of great importance, particularly in the growth of epitaxial monocrystalline CdTe cells. Several substrate materials (CdTe, Si, GaAs, and InSb) have been discussed and all have challenges. These have generally been addressed through the addition of intermediate layers between the substrate and CdTe absorber. InSb is an attractive substrate choice for CdTe devices, because it has a close lattice match with CdTe, it has low resistivity, and it is easy to contact. However, the valence-band alignment between InSb and p-type CdTe, which can both impede hole current and enhance forward electron current, is not favorable. Three strategies to address the band-offset problem are investigated by numerical simulation: (a) heavy doping of the back part of the CdTe layer, (b) incorporation of an intermediate CdMgTe or CdZnTe layer, and (c) formation of an InSb tunnel junction. Each of these strategies is predicted to be helpful for higher cell performance, but a combination of them should be most effective. In addition, the CdTe/back contact interface plays a significant role in carrier transport for conventional polycrystalline thin-film CdTe devices. A significant back-contact barrier φb caused by metallic contact with low work function can block hole transport and enhance the forward current and thus result in a reduced VOC, particularly with fully-depleted CdTe devices. A buffer contact layer between CdTe absorber and metallic contact is strongly needed to mitigate this detrimental impact. The simulation has shown that a thin tellurium (Te) buffer as well as a highly doped p-type CdTe layer can assume such a role by reducing the downward valence-band bending caused by large φb and hence enhancing the extraction of the charge carriers. Finally, experimental CdTe cells are discussed in parallel with the simulation results to identify limiting mechanisms and give guidance for future efficiency improvement. For the monocrystalline CdTe cells made at NREL, it is found that the sputter damage causing large numbers of defect states near the Cd(S,O)/CdTe interface plays an important role in limiting cell performance, particularly for cells with low oxygen Cd(S,O) (with a "cliff" band offset). Other effects, such as the large series resistance and reflection, also reduce the cell performance. A lattice-matched material with less deposition damage and with a type-I interface is suggested to introduce less interfacial recombination in future emitter growth on epitaxial CdTe absorbers. For polycrystalline CdTe solar cells made at CSU, it is demonstrated that an MZO emitter forms a spike at the MZO/CdTe interface and a Te buffer layer mitigates large back-contact barrier φb. Both play very important roles in achieving good cell performance (VOC ~ 860 mV, η ~ 18.3%). The simulation has also shown that the electron reflector would be an effective approach to further increase VOC even with a relative low CdTe carrier concentration (~1014 cm-3).
Keywords: design; epitaxial; thin film; device simulation; CdTe; solar cells