Ferry, Corentin, authorRajopadhye, Sanjay, advisorDerrien, Steven, advisorWilson, Jesse, committee memberPasricha, Sudeep, committee memberMcClurg, Jedidiah, committee memberSadayappan, Ponnuswamy, committee memberde Dinechin, Florent, committee memberCollange, Caroline, committee member2024-05-272024-05-272024https://hdl.handle.net/10217/238480As processors compute power keeps increasing, so do their demands in memory accesses: some computations will require a higher bandwidth and exhibit regular memory access patterns, others will require a lower access latency and exhibit random access patterns. To cope with all demands, memory technologies are becoming diverse. It is then necessary to adapt both programs and hardware accelerators to the memory technology they use. Notably, memory access patterns and memory layouts have to be optimized. Manual optimization can be extremely tedious and does not scale to a large number of processors and memories, where automation becomes necessary. In this Ph.D dissertation, we suggest several automated methods to derive data layouts from programs, notably for FPGA accelerators. We focus on getting the best throughput from high-latency, high-bandwidth memories and, for all kinds of memories, the lowest redundancy while preserving contiguity. To this effect, we introduce mathematical analyses to partition the data flow of a program with uniform and affine dependence patterns, propose memory layouts and automation techniques to get optimized FPGA accelerators.born digitaldoctoral dissertationsengCopyright and other restrictions may apply. User is responsible for compliance with all applicable laws. For information about copyright law, please see https://libguides.colostate.edu/copyright.high-level synthesispolyhedral modelmemorycompilersText