Timing analysis of CMOS logic gates in deep submicron VLSI design - Jiang, Xueping, author; Jayasumana, Anura P., advisor; Chandrasekar, V., committee member; Lile, D. L., committee member; Malaiya, Y. K., committee member (Colorado State University. Libraries, 2005)
A comprehensive timing analysis of complementary metal-oxide semiconductor (CMOS) logic gates in deep submicron very large scale integration (VLSI) design is carried out. A computationally simple proper deep submicron MOSFET model (PDSMM) is proposed to accurately describe the static 1-V characteristics of both long channel and deep submicron metal-oxide semiconductor field effect transistors (MOSFETs). The PDSMM is an extension of Shockley MOSFET model and Shichman-Hodges MOSFET model by incorporating the second-order effects of deep submicron MOSFETs such as charge carrier velocity saturation and channel length modulation. Using the PDSMM we develop propagation delay models for a deep submicron CMOS inverter. The effects of input transition time, gate-to-drain coupling capacitance, parasitic drain diffusion capacitance, and external load capacitance are taken into account. Even in the extreme conditions, the proposed propagation delay model of a deep submicron CMOS inverter can accurately duplicate the propagation delays from SPICE BSIM3. In order to extend the propagation delay methodologies for a deep submicron CMOS inverter to model single-stage complex CMOS logic gates such as NAND or NOR gate, a generic series-connected MOSFET chain model (SMCM) is proposed to accurately depict the peculiar static 1-V characteristics of a series-connected MOSFET chain with an equal input pattern. The effect of initial states of parasitic capacitances of intermediate nodes of a series-connected MOSFET chain is taken into account by using a modified input suppression technique associated with activation time. We focus on fast initial state (FIS) and slow initial state (SIS), which are the most useful in practice. Using the SMCM and the modified input suppression technique we develop propagation delay models for a single-stage complex CMOS logic gate. We propose a simple input mapping technique to investigate the effect of arbitrary input pattern of a single-stage complex CMOS logic gate. These timing models include initial states of parasitic capacitances and arbitrary input pattern in addition to the factors used in propagation delay models of a CMOS inverter. The comprehensive propagation delay models of a single-stage complex CMOS logic gate can accurately reproduce the propagation delays from SPICE BSIM3. The proposed comprehensive propagation delay models are suitable to precisely describe transition behaviors of deep submicron CMOS logic gates. They can be exploited in electronic design automation (EDA) flows to implement, verify and optimize deep submicron CMOS VLSI designs.
Keywords: electrical engineering