Endsley, Neil H., authorGabriel, Arthur R., authorScharf, Louis L., authorBurleson, Wayne P., authorIEEE, publisher2007-01-032007-01-031989Burleson, Wayne, P., et al., A Systolic VLSI Chip for Implementing Orthogonal Transforms, IEEE Journal of Solid-State Circuits 24, no. 2 (April 1989): 466-469.http://hdl.handle.net/10217/735This paper describes the design of a systolic VLSI chip for the implementation of signal processing algorithms that may be decomposed into a product of simple real rotations. These include orthogonal transformations. Applications of this chip include projections, discrete Fourier and cosine transforms, and geometrical transformations. Large transforms may be computed by "tiling" together many chips for increased throughput. A CMOS VLSI chip containing 138 000 transistors in a 5x3 array of rotators has been designed, fabricated, and tested. The chip has a 32-MHz clock and performs real rotations at a rate of 30 MHz. The systolic nature of the chip makes use of fully synchronous bit-serial interconnect and a very regular structure at the rotator and bit levels. A distributed arithmetic scheme is used to implement the matrix-vector multiplication of the rotation.born digitalarticleseng©1989 IEEE.Copyright and other restrictions may apply. User is responsible for compliance with all applicable laws. For information about copyright law, please see https://libguides.colostate.edu/copyright.CMOS integrated circuitsVLSIcellular arrayscomputerised signal processingdigital arithmeticdigital signal processing chipsparallel architecturespipeline processingreal-time systemstransformsText