Ahadi Dolatsara, Majid, authorRoy, Sourajeet, advisorNotaros, Branislav, committee memberAnderson, Chuck, committee memberPezeshki, Ali, committee member2016-08-182016-08-182016http://hdl.handle.net/10217/176722With the scaling of VLSI technology to sub-45 nm levels, uncertainty in the nanoscale manufacturing processes and operating conditions have been found to result in unpredictable circuit behavior at the chip, package, and board levels of modern integrated microsystems. Hence, modeling the forward propagation of uncertainty from the device-level parameters to the system-level response of high-speed circuits and systems forms a crucial requirement of modern computer-aided design (CAD) tools. This thesis presents novel approaches based on the generalized polynomial chaos (gPC) theory for the efficient multidimensional uncertainty quantification of general distributed and lumped high-speed circuit networks. The key feature of this work is the development of approaches which are more efficient and/or accurate comparing to recently suggested uncertainty quantification approaches in the literature. Main contributions of this thesis are development of two individual approaches for improvement of the conventional linear regression uncertainty quantification approach, and development of a sparse polynomial expansion of the stochastic response in an uncertain system. The validity of this work is established through multiple numerical examples.born digitalmasters thesesengCopyright and other restrictions may apply. User is responsible for compliance with all applicable laws. For information about copyright law, please see https://libguides.colostate.edu/copyright.high speed circuitspolynomial chaosuncertainty quantificationlinear regressioncomputer aided designsignal integrityText