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Browsing by Author "Roy, Sourajeet, committee member"

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    Development of reduced polynomial chaos-Kriging metamodel for uncertainty quantification of computational aerodynamics
    (Colorado State University. Libraries, 2018) Weinmeister, Justin, author; Gao, Xinfeng, advisor; Roy, Sourajeet, committee member; Guzik, Stephen, committee member; Alves, Dino, committee member
    Computational fluid dynamics (CFD) simulations are a critical component of the design and development of aerodynamic bodies. However, as engineers attempt to capture more detailed physics, the computational cost of simulations increases. This limits the ability of engineers to use robust or multidisciplinary design methodologies for practical engineering applications because the computational model is too expensive to evaluate for uncertainty quantification studies and off-design performance analysis. Metamodels (surrogate models) are a closed-form mathematical solution fit to only a few simulation responses which can be used to remedy this situation by estimating off-design performance and stochastic responses of the CFD simulation for far less computational cost. The development of a reduced polynomial chaos-Kriging (RPC-K) metamodel is another step towards eliminating simulation gridlock by capturing the relevant physics of the problem in a cheap-to-evaluate metamodel using fewer CFD simulations. The RPC-K metamodel is superior to existing technologies because its model reduction methodology eliminates the design parameters which contribute little variance to the problem before fitting a high-fidelity metamodel to the remaining data. This metamodel can capture non-linear physics due to its inclusion of both the long-range trend information of a polynomial chaos expansion and local variations in the simulation data through Kriging. In this thesis, the RPC-K metamodel is developed, validated on a convection-diffusion-reaction problem, and applied to the NACA 4412 airfoil and aircraft engine nacelle problems. This research demonstrates the metamodel's effectiveness over existing polynomial chaos and Kriging metamodels for aerodynamics applications because of its ability to fit non-linear fluid flows with far fewer CFD simulations. This research will allow aerospace engineers to more effectively take advantage of detailed CFD simulations in the development of next-generation aerodynamic bodies through the use of the RPC-K metamodel to save computational cost.
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    Fast and accurate double-higher-order method of moments accelerated by Diakoptic Domain Decomposition and memory efficient parallelization for high performance computing systems
    (Colorado State University. Libraries, 2015) Manić, Ana, author; Notaros, Branislav, advisor; Reising, Steven, committee member; Oprea, Iuliana, committee member; Roy, Sourajeet, committee member; Ilić, Milan, committee member
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    High performance and energy efficient shared hybrid last level cache architecture in multicore systems
    (Colorado State University. Libraries, 2018) Bhosale, Swapnil, author; Pasricha, Sudeep, advisor; Roy, Sourajeet, committee member; Bohm, Wim, committee member
    As the performance gap between CPU and main memory continues to increase, it causes a significant roadblock to exascale computing. Memory performance has not kept up with CPU performance, and is becoming a bottleneck today, particularly due to the advent of data-intensive applications. To accommodate the vast amount of data required by these applications, emerging non-volatile memory technology STTRAM (Spin-Transfer Torque Random Access Memory) is a good candidate to replace or augment SRAM from last-level cache (LLC) memory because of its high capacity, good scalability, and low power consumption. However, its expensive write operations prevent it from becoming a universal memory candidate. In this thesis, we propose an SRAM-STTRAM hybrid last level cache (LLC) architecture that consumes less energy and performs better than SRAM-only and STTRAM-only LLC. We design an algorithm to reduce write operations to the STTRAM region of the hybrid LLC and consequently minimize the write energy of STTRAM. Compared to two prior state-of-the-art techniques, our proposed technique achieves 29.23% and 5.94% total LLC energy savings and 6.863% and 0.407% performance improvement for various SPLASH2 and PARSEC parallel benchmarks.
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    Reliability-aware and energy-efficient system level design for networks-on-chip
    (Colorado State University. Libraries, 2015) Zou, Yong, author; Pasricha, Sudeep, advisor; Roy, Sourajeet, committee member; Chen, Tom, committee member; Bohm, Wim, committee member
    With CMOS technology aggressively scaling into the ultra-deep sub-micron (UDSM) regime and application complexity growing rapidly in recent years, processors today are being driven to integrate multiple cores on a chip. Such chip multiprocessor (CMP) architectures offer unprecedented levels of computing performance for highly parallel emerging applications in the era of digital convergence. However, a major challenge facing the designers of these emerging multicore architectures is the increased likelihood of failure due to the rise in transient, permanent, and intermittent faults caused by a variety of factors that are becoming more and more prevalent with technology scaling. On-chip interconnect architectures are particularly susceptible to faults that can corrupt transmitted data or prevent it from reaching its destination. Reliability concerns in UDSM nodes have in part contributed to the shift from traditional bus-based communication fabrics to network-on-chip (NoC) architectures that provide better scalability, performance, and utilization than buses. In this thesis, to overcome potential faults in NoCs, my research began by exploring fault-tolerant routing algorithms. Under the constraint of deadlock freedom, we make use of the inherent redundancy in NoCs due to multiple paths between packet sources and sinks and propose different fault-tolerant routing schemes to achieve much better fault tolerance capabilities than possible with traditional routing schemes. The proposed schemes also use replication opportunistically to optimize the balance between energy overhead and arrival rate. As 3D integrated circuit (3D-IC) technology with wafer-to-wafer bonding has been recently proposed as a promising candidate for future CMPs, we also propose a fault-tolerant routing scheme for 3D NoCs which outperforms the existing popular routing schemes in terms of energy consumption, performance and reliability. To quantify reliability and provide different levels of intelligent protection, for the first time, we propose the network vulnerability factor (NVF) metric to characterize the vulnerability of NoC components to faults. NVF determines the probabilities that faults in NoC components manifest as errors in the final program output of the CMP system. With NVF aware partial protection for NoC components, almost 50% energy cost can be saved compared to the traditional approach of comprehensively protecting all NoC components. Lastly, we focus on the problem of fault-tolerant NoC design, that involves many NP-hard sub-problems such as core mapping, fault-tolerant routing, and fault-tolerant router configuration. We propose a novel design-time (RESYN) and a hybrid design and runtime (HEFT) synthesis framework to trade-off energy consumption and reliability in the NoC fabric at the system level for CMPs. Together, our research in fault-tolerant NoC routing, reliability modeling, and reliability aware NoC synthesis substantially enhances NoC reliability and energy-efficiency beyond what is possible with traditional approaches and state-of-the-art strategies from prior work.
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    Reliable, energy-efficient, and secure silicon photonic network-on-chip design for manycore architectures
    (Colorado State University. Libraries, 2018) Chittamuru, Sai Vineel Reddy, author; Pasricha, Sudeep, advisor; Jayasumana, Anura, committee member; Roy, Sourajeet, committee member; Malaiya, Yashwant K., committee member
    Advances in technology scaling over the past s+H91everal decades have enabled the integration of billions of transistors on a single die. Such a massive number of transistors has allowed multiple processing cores and significant memory to be integrated on a chip, to meet the rapidly growing performance demands of modern applications. These on-chip processing and memory components require an efficient mechanism to communicate with each other. Thus emerging manycore architectures with high core counts have adopted scalable packet switched electrical network-on-chip (ENoC) fabrics to support on-chip transfers. But with several hundreds to thousands of on-chip cores expected to become a reality in the near future, ENoCs are projected to suffer from cripplingly high power dissipation and limited performance. Recent developments in the area of silicon photonics have enabled the integration of on-chip photonic interconnects with CMOS circuits, enabling photonic networks-on-chip (PNoCs) that can offer ultra-high bandwidth, reduced power dissipation, and lower latency than ENoCs. There are several challenges that hinder the commercial adoption of these PNoC architectures. Especially, the operation of silicon photonic components is very sensitive to thermal variations (TV) and process variations (PV) that frequently occur on a chip. These variations and their mitigation techniques create significant reliability issues and increase energy costs in PNoCs. Furthermore, photonic components are susceptible to intrinsic crosstalk noise and aging, which demands higher energy for reliable communication. Moreover, contention in photonic waveguides as well as laser power distribution overheads also reduce performance and energy-efficiency. In addition, hardware trojans (HTs) in the electrical circuitry of photonic components lead to covert data snooping from shared photonic waveguides and introduces serious hardware security threats. To address these challenges, in this dissertation we propose a cross-layer framework towards the design of reliable, secure, and energy-efficient PNoC architectures. We devise layer-specific solutions for PNoC design as part of our framework: (i) we propose device-level enhancements to adapt to TV, and to mitigate heterodyne crosstalk and intermodulation effect induced heterodyne crosstalk; we also analyze aging in photonic components and explore its impact on PNoCs; (ii) at the circuit-level we propose PV-aware homodyne and heterodyne crosstalk mitigation mechanisms, a PV-aware security enhancement mechanism, and TV- and PV-aware photonic component assignment mechanisms; (iii) at the architecture-level we propose new application specific and reconfigurable PNoC architectures to improve photonic channel utilization, a laser power management scheme across components of PNoC architectures, and a reservation-assisted security enhancement scheme to improve security in PNoC architectures; and (iv) at the system-level we propose TV and PV aware thread migration schemes and application scheduling schemes that exploit adaptive application degree of parallelism (DoP). In addition to layer-specific enhancements, we also combine techniques across layers to create cross-layer optimization strategies to aggressively improve reliability and energy-efficiency in PNoC architectures. In our SPECTRA and LIBRA frameworks we combine system-level and circuit-level enhancements for TV management in PNoCs. In our 'Island of Heater' framework we combine system-level and device-level enhancements for TV management in PNoCs. We combine device-level and circuit-level enhancements for heterodyne crosstalk mitigation in our PICO and HYDRA frameworks. Our proposed BiGNoC architecture uses architectural-level enhancements and system-level application scheduling to improve its performance and energy-efficiency. Lastly, in our SOTERIA framework we combine circuit-level and architecture-level enhancements to enable secure communication in DWDM-based PNoC architectures.
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    Smart indoor localization using machine learning techniques
    (Colorado State University. Libraries, 2014) Ugave, Viney Anand, author; Pasricha, Sudeep, advisor; Anderson, Charles, committee member; Roy, Sourajeet, committee member
    The advancement of smartphone devices has led to a generation of new applications and solutions. These devices give away a great deal of information about the user (location, posture, communication patterns, etc.), which helps in capturing the user's context. Such information can be utilized to create smarter apps from which the user can benefit. A challenging new area that is receiving a lot of attention is Indoor Localization whereas interest in location-based services is also rising. While numerous smartphone based indoor localization techniques have been proposed, these techniques have many shortcomings related to accuracy and consistency. More importantly, these techniques entail high-energy consumption that can quickly drain a smartphone battery. In this thesis, we propose innovative techniques based on machine learning algorithms and smart sensor management for effective Indoor Localization using smartphones. We evaluated our techniques on several indoor environments with diverse characteristics and show improvements over several state-of-the-art techniques from prior work. The extensive use of sensors and Wi-Fi scans can deplete the smartphone battery and so we quantitatively accounted for all the modules that consume the battery power. We also performed energy and accuracy tradeoff analysis to provide a broader understanding of how to smartly use these techniques. Furthermore, we investigated, implemented and tested both sensor and machine learning based techniques. Our best technique achieved an average accuracy between 1-3 meters across most of our evaluated indoor paths.