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Browsing by Author "Malaiya, Yashwant K., committee member"

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    A simple and dynamic data structure for pattern matching in texts
    (Colorado State University. Libraries, 2011) Woo, Sung-Whan, author; McConnell, Ross M., advisor; Bohm, A. P. Willem, committee member; Penttila, Tim, committee member; Malaiya, Yashwant K., committee member
    The demand for a pattern matching algorithm is currently on the rise from diverse areas such as string search, image matching, voice recognition and bioinformatics. In particular, string search or matching algorithms have been growing in popularity as they have been applied to areas such as text editors, search engines and bioinformatics. To satisfy these various demands, many string matching methods have been developed to search for substrings (pattern strings) within a text, and several techniques employ the use of tree data structures, deterministic finite automata, and other structures. The problem of string matching is defined by finding all location of a pattern string P within a text T, where preprocessing of T is allowed in order to facilitate the queries. There has been significant success in finding a pattern string in O(m+k) time, where m is the length of the pattern string and k is the number of occurrences, using data structures that can be constructed in O(n) time, where n is the length of T. Suffix trees and directed acyclic word graphs are such data structures. All of these data structures index the searched text in O(m+k) time. However, the difficulty of understanding and programming the construction algorithms is rarely mentioned. Also, they have significant space requirements and take Θ(n) time to update even if one character of T is changed. To solve these problems, we propose the augmented position heap. It can be built in O(n) time, and can be used to search a pattern string in O(m+k) time. Most importantly, when a block of j characters are inserted or deleted, the asymptotic updating it when a text is modified is O((h(T) + j)h(T)), where h(T) is the length of the longest substring X of T that occurs at least
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    A systematic approach to testing UML designs
    (Colorado State University. Libraries, 2006) Dinh-Trong, Trung T., author; France, Robert B., advisor; Ghosh, Sudipto, advisor; Bieman, James M., committee member; Malaiya, Yashwant K., committee member; Fan, Chuen-mei, committee member
    In Model Driven Engineering (MDE) approaches, developers create and refine design models from which substantial portions of implementations are generated. During refinement, undetected faults in abstract model can traverse into the refined model, and eventually into code. Hence, finding and removing faults in design models is essential for MDE approaches to succeed. This dissertation describes approach to finding faults in design models created using the Unified Modeling Language (UML). Executable forms of UML design models are exercised using generated test inputs that provide coverage with respect to UML-based coverage criteria. The UML designs that are tested consist of class diagrams, sequence diagrams and activity diagrams. The contribution of the dissertation includes (1) a test input generation technique, (2) an approach to execute design models describing sequential behavior with test inputs in order to detect faults, and (3) a set of pilot studies that are carried out to explore the fault detection capability of our testing approach. The test input generation technique involves analyzing design models under test to produce test inputs that satisfy UML sequence diagram coverage criteria. We defined a directed graph structure, named Variable Assignment Graph (VAG), to generate test inputs. The VAG combines information from class and sequence diagrams. Paths are selected from the VAG and constraints are identified to traverse the paths. The constraints are then solved with a constraint solver. The model execution technique involves transforming each design under test into an executable from, which is exercised with the general inputs. Failures are reported if the observed behavior differs from the expected behavior. We proposed an action language, named Java-like Action Language (JAL), that supports the UML action semantics. We developed a prototype tool, named UMLAnT, that performs test execution and animation of design models. We performed pilot studies to evaluate the fault detection effectiveness of our approach. Mutation faults and commonly occurring faults in UML models created by students in our software engineering courses were seeded in three design models. Ninety percent of the seeded faults were detected using our approach.
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    A unified modeling language framework for specifying and analyzing temporal properties
    (Colorado State University. Libraries, 2018) Al Lail, Mustafa, author; France, Robert B., advisor; Ray, Indrakshi, advisor; Ray, Indrajit, committee member; Hamid, Idris Samawi, committee member; Malaiya, Yashwant K., committee member
    In the context of Model-Driven Engineering (MDE), designers use the Unified Modeling Language (UML) to create models that drive the entire development process. Once UML models are created, MDE techniques automatically generate code from the models. If the models have undetected faults, they are propagated to code where they require considerable time and effort to detect and correct. It is therefore mandatory to analyze UML models at earlier stages of the development life-cycle to ensure the success of the MDE techniques in producing reliable software. One approach to uncovering design errors is to formally specify and analyze the properties that a system has to satisfy. Although significant research appears in specifying and analyzing properties, there is not an effective and efficient UML-based framework that specifies and analyzes temporal properties. The contribution of this dissertation is a UML-based framework and tools for aiding UML designers to effectively and efficiently specify and analyze temporal properties. In particular, the framework is composed of 1) a UML specification technique that designers can use to specify temporal properties, 2) a rigorous analysis technique for analyzing temporal properties, 3) an optimization technique to scale the analysis to large class models, and 4) a proof-of-concept tool. An evaluation of the framework using two real-world studies shows that the specification technique can be used to specify a variety of temporal properties and the analysis technique can uncover certain types of design faults. It also demonstrates that the optimization technique can significantly speed up the analysis.
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    An outlier detection approach for PCB testing based on Principal Component Analysis
    (Colorado State University. Libraries, 2011) He, Xin, author; Jayasumana, Anura P., advisor; Malaiya, Yashwant K., committee member; Reising, Steven C., committee member
    Capacitive Lead Frame Testing, a widely used approach for printed circuit board testing, is very effective for open solder detection. The approach, however, is affected by mechanical variations during testing and by tolerances of electrical parameters of components, making it difficult to use threshold based techniques for defect detection. A novel approach is presented in this thesis for identifying boardruns that are likely to be outliers. Based on Principal Components Analysis (PCA), this approach treats the set of capacitance measurements of individual connectors or sockets in a holistic manner to overcome the measurement and component parameter variations inherent in test data. Effectiveness of the method is evaluated using measurements on different types of boards. Based on multiple analyses of different measurement datasets, the most suitable statistics for outlier detection and relative parameter values are also identified. Enhancements to the PCA-based technique using the concept of test-pin windows are presented to increase the resolution of the analysis. When applied to one test window at a time, PCA is able to detect the physical position of potential defects. Combining the basic and enhanced techniques, the effectiveness of outlier detection is improved. The PCA based approach is extended to detect and compensate for systematic variation of measurement data caused by tilt or shift of the sense plate. This scheme promises to enhance the accuracy of outlier detection when measurements are from different fixtures. Compensation approaches are introduced to correct the 'abnormal' measurements due to sense-plate variations to a 'normal' and consistent baseline. The effectiveness of this approach in the presence of the two common forms of mechanical variations is illustrated. Potential to use PCA based analysis to estimate the relative amount of tilt and shift in sense plate is demonstrated.
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    Applications of inertial measurement units in monitoring rehabilitation progress of arm in stroke survivors
    (Colorado State University. Libraries, 2011) Doshi, Saket Sham, author; Jayasumana, Anura P., advisor; Malcolm, Matthew P., committee member; Pasricha, Sudeep, committee member; Malaiya, Yashwant K., committee member
    Constraint Induced Movement Therapy (CIMT) has been clinically proven to be effective in restoring functional abilities of the affected arm among stroke survivors. Current CIMT delivery method lacks a robust technique to monitor rehabilitation progress, which results in increasing costs of stroke related health care. Recent advances in the design and manufacturing of Micro Electro Mechanical System (MEMS) inertial sensors have enabled tracking human motions reliably and accurately. This thesis presents three algorithms that enable monitoring of arm movements during CIMT by means of MEMS inertial sensors. The first algorithm quantifies the affected arm usage during CIMT. This algorithm filters the arm movement data, sampled during activities of daily life (ADL), by applying a threshold to determine the duration of affected arm movements. When an activity is performed multiple times, this algorithm counts the number of repetitions performed. Current technique uses a touch/proximity sensor and a motor activity log maintained by the patient to determine CIMT duration. Affected arm motion is a direct indicator of CIMT session and hence this algorithm tracks rehabilitation progress more accurately. Actual patients' affected arm movement data analysis shows that the algorithm does activity detection with an average accuracy of >90%. Second of the three algorithms, tracking stroke rehabilitation of affected arm through histogram of distance traversed, evaluates an objective metric to assess rehabilitation progress. The objective metric can be used to compare different stroke patients based on their functional ability in affected arm. The algorithm calculates the histogram by evaluating distances traversed over a fixed duration window. The impact of this window on algorithm's performance is analyzed. The algorithm has better temporal resolution when compared with another standard objective test, box and block test (BBT). The algorithm calculates linearly weighted area under the histogram as a score to rank various patients as per their rehabilitation progress. The algorithm has better performance for patients with chronic stroke and certain degree of functional ability. Lastly, Kalman filter based motion tracking algorithm is presented that tracks linear motions in 2D, such that only one axis can experience motion at any given time. The algorithm has high (>95%) accuracy. Data representing linear human arm motion along a single axis is generated to analyze and determine optimal parameters of Kalman filter. Cross-axis sensitivity of the accelerometer limits the performance of the algorithm over longer durations. A method to identify the 1D components of 2D motion is developed and cross-axis effects are removed to improve the performance of motion tracking algorithm.
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    COVID-19 misinformation on Twitter: the role of deceptive support
    (Colorado State University. Libraries, 2022) Hashemi Chaleshtori, Fateme, author; Ray, Indrakshi, advisor; Anderson, Charles W., committee member; Malaiya, Yashwant K., committee member; Adams, Henry, committee member
    Social media platforms like Twitter are a major dissemination point for information and the COVID-19 pandemic is no exception. But not all of the information comes from reliable sources, which raises doubts about their validity. In social media posts, writers reference news articles to gain credibility by leveraging the trust readers have in reputable news outlets. However, there is not always a positive correlation between the cited article and the social media posting. Targeting the Twitter platform, this study presents a novel pipeline to determine whether a Tweet is indeed supported by the news article it refers to. The approach follows two general objectives: to develop a model capable of detecting Tweets containing claims that are worthy of fact-checking and then, to assess whether the claims made in a given Tweet are supported by the news article it cites. In the event that a Tweet is found to be trustworthy, we extract its claim via a sequence labeling approach. In doing so, we seek to reduce the noise and highlight the informative parts of a Tweet. Instead of detecting erroneous and invalid information by analyzing the propagation patterns or ensuing examination of Tweets against already proven statements, this study aims to identify reliable support (or lack thereof) before misinformation spreads. Our research reveals that 14.5% of the Tweets are not factual and therefore not worth checking. An effective filter like this is especially useful when looking at a platform such as Twitter, where hundreds of thousands of posts are created every day. Further, our analysis indicates that among the Tweets which refer to a news article as evidence of a factual claim, at least 1% of those Tweets are not substantiated by the article, and therefore mislead the reader.
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    Design and analysis of energy-efficient hierarchical electro-photonic network-on-chip architectures
    (Colorado State University. Libraries, 2015) Desai, Srinivas, author; Pasricha, Suddep, advisor; Rajopadhye, Sanjay, committee member; Malaiya, Yashwant K., committee member
    Future applications running on chip multiprocessors (CMPs) with tens to hundreds of cores on a chip will require an efficient inter-core communication strategy to achieve high performance. With recent demonstrations of feasibility in fabricating photonic components for on-chip communication, researchers are now focusing on photonic communication based on-chip networks for future CMPs. Photonic interconnects offer several benefits over conventional electrical on-chip interconnects, such as (1) high-bandwidth support by making use of dense wavelength division multiplexing, (2) distance independent power consumption, (3) significantly lower latency, and (4) improved performance-per-watt. Owing to these advantages, photonic interconnects are being considered as worthy alternatives for existing electrical networks. In this thesis, we design and explore a hierarchical electro-photonic network-on-chip (NoC) architecture called NOVA. NOVA aims to optimize several key design metrics such as throughput, latency, energy-delay-product, and power, which determine the overall system performance of a CMP. NOVA has three levels of communication hierarchy. The first level has a broadband-resonator based photonic switch. The second level consists of a low-loss, silicon-nitride arrayed waveguide grating based router. The last level of the hierarchy is made up of photonic ring waveguides. We have modeled and simulated multiple configurations of the proposed architecture with different designs of the photonic switch and several arbitration techniques on the photonic rings. This comprehensive analysis of NOVA allows us to arrive at an optimal configuration of the network for a given set of input applications and CMP platform. Finally, experimental results are strong indicators for considering the proposed architecture, as the improvements achieved were up to 6.1×, 55%, 5×, and 5.9× in terms of throughput, latency, energy-delay-product, and power compared to other state-of-the-art photonic NoC architectures.
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    Hardware-software codesign of silicon photonic AI accelerators
    (Colorado State University. Libraries, 2024) Sunny, Febin P., author; Pasricha, Sudeep, advisor; Nikdast, Mahdi, advisor; Chen, Haonen, committee member; Malaiya, Yashwant K., committee member
    Machine learning applications have become increasingly prevalent over the past decade across many real-world use cases, from smart consumer electronics to automotive, healthcare, cybersecurity, and language processing. This prevalence has been fueled by the emergence of powerful machine learning models, such as Deep Neural Networks (DNNs), Convolutional Neural Networks (CNNs), and Recurrent Neural Networks (RNNs). As researchers explore deeper models with higher connectivity, the computing power and the memory requirement necessary to train and utilize them also increase. Such increasing complexity also necessitates that the underlying hardware platform should consistently deliver better performance while satisfying strict power constraints. Unfortunately, the limited performance-per-watt in today's computing platforms – such as general-purpose CPUs, GPUs, and electronic neural network (NN) accelerators – creates significant challenges for the growth of new deep learning and AI applications. These electronic computing platforms face fundamental limits in the post-Moore Law era due to increased ohmic losses and capacitance-induced latencies in interconnects, as well as power inefficiencies and reliability concerns that reduce yields and increase costs with semiconductor-technology scaling. A solution to improving performance-per-watt for AI model processing is to explore more efficient hardware NN accelerator platforms. Silicon photonics has shown promise in terms of achievable energy efficiency and latency for data transfers. It is also possible to use photonic components to perform computation, e.g., matrix-vector multiplication. Such photonics-based AI accelerators can not only address the fan-in and fan-out problem with linear algebra processors, but their operational bandwidth can approach the photodetection rate (typically in the hundreds of GHz), which is orders of magnitude higher than electronic systems today that operate at a clock rate of a few GHz. A solution to the data-movement bottleneck can be the use of silicon photonics technology for photonic networks-on-chip (PNoCs), which can enable ultra-high bandwidth, low latency, and energy-efficient communication. However, to ensure reliable, efficient, and high throughput communication and computation using photonics, several challenges must be addressed first. Photonic computation is performed in the analog domain, which makes it susceptible to various noise sources and drives down the achievable resolution for representing NN model parameters. To increase the reliability of silicon photonic AI accelerators, fabrication-process variation (FPV), which is the change in physical dimensions and characteristics of devices due to imperfections in fabrication, must be addressed. FPVs induce resonant wavelength shifts that need to be compensated, for the microring resonators (MRs), which are the fundamental devices to realize photonic computation and communication in our proposed accelerator architectures, to operate correctly. Without this correction, FPVs will cause increased crosstalk and data corruption during photonic communication and can also lead to errors during photonic computation. Accordingly, the correction for FPVs is an essential part of reliable computation in silicon photonic-based AI accelerators. Even with FPV-resilient silicon photonic devices, the tuning latency incurred by thermo-optic (TO) tuning and the thermal crosstalk it can induce are significant. The latency, which can be in the microsecond range, impacts the overall throughput of the accelerator and the thermal crosstalk impacts its reliable operation. At the architectural level it is also necessary to ensure that the NN processing is done efficiently while making use of the photonic resources in terms of wavelengths, and NN model-aware decisions in terms of device deployment, arrangement, and multiply and accumulate (MAC) unit design have to be performed. To address these challenges, the major contributions of this thesis are focused on proposing a hardware-software co-design framework to enable high throughput, low latency, and energy-efficient AI acceleration across various neural network models, using silicon photonics. At the architectural level, we have proposed wavelength reuse schemes, vector decomposition, and NN-aware MAC unit designs for increased efficiency in laser power consumption. In terms of NN-aware designs, we have proposed layer-specific acceleration units, photonic batch normalization folding, and fine-grained sparse NN acceleration units. To tackle the reliability challenges introduced by FPV, we have performed device-level design-space exploration and optimization to design MRs that are more tolerant to FPVs than the state-of-the-art efforts in this area. We also adapt Thermal Eigen-mode decomposition and have devised various novel techniques to manage thermal and spectral crosstalk sources, allowing our silicon photonic-based AI accelerators to reach up to 16-bit parameter resolution per MR, which enables high accuracy for most NN models.
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    Impact of resequencing buffer distribution on packet reordering
    (Colorado State University. Libraries, 2011) Mandyam Narasiodeyar, Raghunandan, author; Jayasumana, Anura P., advisor; Malaiya, Yashwant K., committee member; Pasricha, Sudeep, committee member
    Packet reordering in Internet has become an unavoidable phenomenon wherein packets get displaced during transmission resulting in out of order packets at the destination. Resequencing buffers are used at the end nodes to recover from packet reordering. This thesis presents analytical estimation methods for "Reorder Density" (RD) and "Reorder Buffer occupancy Density" (RBD) that are metrics of packet reordering, of packet sequences as they traverse through resequencing nodes with limited buffers. During the analysis, a "Lowest First Resequencing Algorithm" is defined and used in individual nodes to resequence packets back into order. The results are obtained by studying the patterns of sequences as they traverse through resequencing nodes. The estimations of RD and RBD are found to vary for sequences containing different types of packet reordering patterns such as Independent Reordering, Embedded Reordering and Overlapped Reordering. Therefore, multiple estimations in the form of theorems catering to different reordering patterns are presented. The proposed estimation models assist in the allocation of resources across intermediate network elements to mitigate the effect of packet reordering. Theorems to derive RBD from RD when only RD is available are also presented. Just like the resequencing estimation models, effective RBD for a given RD are also found to vary for different packet reordering patterns, therefore, multiple theorems catering to different patterns are presented. Such RBD estimations would be useful for allocating resources based on certain QoS criteria wherein one of the metrics is RD. Simulations driven by Internet measurement traces and random sequences are used to verify the analytical results. Since high degree of packet reordering is known to affect the quality of applications using TCP and UDP on the Internet, this study has broad applicability in the area of mobile communication and networks.
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    Kuwaiti engineers' perspectives of the engineering senior design (capstone) course as related to their professional experiences
    (Colorado State University. Libraries, 2010) AlSagheer, Abdullah, author; Quick, Donald Gene, advisor; Anderson, Sharon K., committee member; Banning, James H., committee member; Malaiya, Yashwant K., committee member
    This study looks into transfer of learning and its application in the actual employment of engineering students after graduation. At Kuwait University, a capstone course is being offered that aims to ensure that students amalgamate all kinds of engineering skills to apply to their work. Within a basic interpretive, qualitative study-design methodology, I interviewed 12 engineers who have recently experienced the senior design course at Kuwait University and are presently working in industry. From the analysis, four basic themes emerged that further delineate the focus of the entire study. The themes are 1) need for the capstone course, 2) applicability of and problems with the capstone course, 3) industry problems with training, and 4) students' attitudes toward the capstone course. The study concludes that participants are not transferring engineering skills; rather, they are transferring all types of instructions they have been given during their course of study at the university. A frequent statement is that the capstone course should be improved and specifically that it is necessary to improve upon the timing, schedule, teachers' behavior, contents, and format. The study concludes that Kuwaiti engineers on the whole face problems with time management and management support. The study includes some implications for Kuwait University and recommendations that can provide significant support for the development of the Senior Design (Capstone) Course. For examples: the project must be divided into phases to ensure timely completion of deliverables. In order to motivate students for hard work and to achieve true transfer of learning, Kuwait University is required to communicate with certain organizations to place its students at their research centers for capstone projects. All universities, including Kuwait University, should hire faculty specifically to run the capstone course. In conclusion, the study includes some suggestions for further research studies focused on issues related to the Senior Design (Capstone) Course. Future researchers should focus on developing the project-based course in earlier stages of students' educational program by investigating more about the relationship between student achievement and the market demand.
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    Phishing detection using machine learning
    (Colorado State University. Libraries, 2021) Shirazi, Hossein, author; Ray, Indrakshi, advisor; Anderson, Chuck, advisor; Malaiya, Yashwant K., committee member; Wang, Haonan, committee member
    Our society, economy, education, critical infrastructure, and other aspects of our life have become largely dependent on cyber technology. Thus, cyber threats now endanger various aspects of our daily life. Phishing attacks, even with sophisticated detection algorithms, are still the top Internet crime by victim count in 2020. Adversaries learn from their previous attempts to (i) improve attacks and lure more victims and (ii) bypass existing detection algorithms to steal user's identities and sensitive information to increase their financial gain. Machine learning appears to be a promising approach for phishing detection and, classification algorithms distinguish between legitimate and phishing websites. While machine learning algorithms have shown promising results, we observe multiple limitations in existing algorithms. Current algorithms do not preserve the privacy of end-users due to inquiring third-party services. There is a lack of enough phishing samples for training machine learning algorithms and, over-represented targets have a bias in existing datasets. Finally, adversarial sampling attacks degrade the performance of detection models. We propose four sets of solutions to address the aforementioned challenges. We first propose a domain-name-based phishing detection solution that focuses solely on the domain name of websites to distinguish phishing websites from legitimate ones. This approach does not use any third-party services and preserves the privacy of end-users. We then propose a fingerprinting algorithm that consists of finding similarities (using both visual and textual characteristics) between a legitimate targeted website and a given suspicious website. This approach addresses the issue of bias towards over-represented samples in the datasets. Finally, we explore the effect of adversarial sampling attacks on phishing detection algorithms in-depth, starting with feature manipulation strategies. Results degrade the performance of the classification algorithm significantly. In the next step, we focus on two goals of improving the performance of classification algorithms by increasing the size of used datasets and making the detection algorithm robust against adversarial sampling attacks using an adversarial autoencoder.
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    Reliable, energy-efficient, and secure silicon photonic network-on-chip design for manycore architectures
    (Colorado State University. Libraries, 2018) Chittamuru, Sai Vineel Reddy, author; Pasricha, Sudeep, advisor; Jayasumana, Anura, committee member; Roy, Sourajeet, committee member; Malaiya, Yashwant K., committee member
    Advances in technology scaling over the past s+H91everal decades have enabled the integration of billions of transistors on a single die. Such a massive number of transistors has allowed multiple processing cores and significant memory to be integrated on a chip, to meet the rapidly growing performance demands of modern applications. These on-chip processing and memory components require an efficient mechanism to communicate with each other. Thus emerging manycore architectures with high core counts have adopted scalable packet switched electrical network-on-chip (ENoC) fabrics to support on-chip transfers. But with several hundreds to thousands of on-chip cores expected to become a reality in the near future, ENoCs are projected to suffer from cripplingly high power dissipation and limited performance. Recent developments in the area of silicon photonics have enabled the integration of on-chip photonic interconnects with CMOS circuits, enabling photonic networks-on-chip (PNoCs) that can offer ultra-high bandwidth, reduced power dissipation, and lower latency than ENoCs. There are several challenges that hinder the commercial adoption of these PNoC architectures. Especially, the operation of silicon photonic components is very sensitive to thermal variations (TV) and process variations (PV) that frequently occur on a chip. These variations and their mitigation techniques create significant reliability issues and increase energy costs in PNoCs. Furthermore, photonic components are susceptible to intrinsic crosstalk noise and aging, which demands higher energy for reliable communication. Moreover, contention in photonic waveguides as well as laser power distribution overheads also reduce performance and energy-efficiency. In addition, hardware trojans (HTs) in the electrical circuitry of photonic components lead to covert data snooping from shared photonic waveguides and introduces serious hardware security threats. To address these challenges, in this dissertation we propose a cross-layer framework towards the design of reliable, secure, and energy-efficient PNoC architectures. We devise layer-specific solutions for PNoC design as part of our framework: (i) we propose device-level enhancements to adapt to TV, and to mitigate heterodyne crosstalk and intermodulation effect induced heterodyne crosstalk; we also analyze aging in photonic components and explore its impact on PNoCs; (ii) at the circuit-level we propose PV-aware homodyne and heterodyne crosstalk mitigation mechanisms, a PV-aware security enhancement mechanism, and TV- and PV-aware photonic component assignment mechanisms; (iii) at the architecture-level we propose new application specific and reconfigurable PNoC architectures to improve photonic channel utilization, a laser power management scheme across components of PNoC architectures, and a reservation-assisted security enhancement scheme to improve security in PNoC architectures; and (iv) at the system-level we propose TV and PV aware thread migration schemes and application scheduling schemes that exploit adaptive application degree of parallelism (DoP). In addition to layer-specific enhancements, we also combine techniques across layers to create cross-layer optimization strategies to aggressively improve reliability and energy-efficiency in PNoC architectures. In our SPECTRA and LIBRA frameworks we combine system-level and circuit-level enhancements for TV management in PNoCs. In our 'Island of Heater' framework we combine system-level and device-level enhancements for TV management in PNoCs. We combine device-level and circuit-level enhancements for heterodyne crosstalk mitigation in our PICO and HYDRA frameworks. Our proposed BiGNoC architecture uses architectural-level enhancements and system-level application scheduling to improve its performance and energy-efficiency. Lastly, in our SOTERIA framework we combine circuit-level and architecture-level enhancements to enable secure communication in DWDM-based PNoC architectures.
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    Streamlining decentralized ledger: enhancing historical data access in Hyperledger Fabric
    (Colorado State University. Libraries, 2024) Bachinin, Andrei, author; Ray, Indrakshi, advisor; Malaiya, Yashwant K., committee member; Ray, Indrajit, committee member; Simske, Steven J., committee member
    This thesis presents design and implementation of Indexing Solution (IS) that aims to enhance query retrieval process in Hyperledger Fabric (HLF). In order to address limitations of HLF, we introduce new indexing algorithms: the Version-Based Index (VBI) and the Block-Based Index (BBI). We also introduce several previously unsupported query APIs: GetHistoryForVersionRange (GHFVR), GetHistoryForBlockRange (GHVBR), GetHistoryForKeyRange (GHFKR). All the work we propose is designed to integrate and work seamlessly with HLF, ensuring full backward compatibility with existing architecture. Our experiments demonstrates that proposed solution significantly outperforms original HLF regarding query execution time, reducing it from 6.621 seconds to 0.019 seconds for certain queries. While VBI and BBI introduce a space index overhead, it remains comparable to the space overhead shown in HLF. Furthermore, we adopt parallel data insertion that mitigates a slower data insertion observed in both VBI and BBI. Comparison with traditional database systems (LevelDB and MySQL) and other blockchain solution from literature (Lineage Chain and vChain+) highlights significant advantage of our IS in terms of querying capabilities, paving the way for broader application of HLF.
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    Testing with state variable data-flow criteria for aspect-oriented programs
    (Colorado State University. Libraries, 2011) Wedyan, Fadi, author; Ghosh, Sudipto, advisor; Bieman, James M., committee member; Malaiya, Yashwant K., committee member; Vijayasarathy, Leo, committee member
    Data-flow testing approaches have been used for procedural and object-oriented (OO) programs, and empirically shown to be effective in detecting faults. However, few such approaches have been proposed for aspect-oriented (AO) programs. In an AO program, data-flow interactions can occur between the base classes and aspects, which can affect the behavior of both. Faults resulting from such interactions are hard to detect unless the interactions are specifically targeted during testing. In this research, we propose a data-flow testing approach for AO programs. In an AO program, an aspect and a base class interact either through parameters passed from advised methods in the base class to the advice, or by the direct reading and writing of the base class state variables in the advice. We identify a group of def-use associations (DUAs) that are based on the base class state variables and propose a set of data-flow test criteria that require executing these DUAs. We identify fault types that result from incorrect data-flow interactions in AO programs and extend an existing AO fault model to include these faults. We implemented our approach in a tool that identifies the targeted DUAs by the proposed criteria, runs a test suite, and computes the coverage results. We conducted an empirical study that compares the cost and effectiveness of the proposed criteria with two control-flow criteria. The empirical study is performed using four subject programs. We seeded faults in the programs using three mutation tools, AjMutator, Proteum/AJ, and μJava. We used a test generation tool, called RANDOOP, to generate a pool of random test cases. To produce a test suite that satisfies a criterion, we randomly selected test cases from the test pool until required coverage for a criterion is reached. We evaluated three dimensions of the cost of a test criterion. The first dimension is the size of a test suite that satisfies a test criterion, which we measured by the number of test cases in the test suite. The second cost dimension is the density of a test case which we measured by the number of test cases in the test suite divided by the number of test requirements. The third cost dimension is the time needed to randomly obtain a test suite that satisfies a criterion, which we measured by (1) the number of iterations required by the test suites generator for randomly selecting test cases from a pool of test cases until a test criterion is satisfied, and (2) the number of the iterations per test requirement. Effectiveness is measured by the mutation scores of the test suites that satisfy a criterion. We evaluated effectiveness for all faults and for each fault type. Our results show that the test suites that cover all the DUAs of state variables are more effective in revealing faults than the control-flow criteria. However, they cost more in terms of test suite size and effort. The results also show that the test suites that cover state variable DUAs in advised classes are suitable for detecting most of the fault types in the revised AO fault model. Finally, we evaluated the cost-effectiveness of the test suites that cover all state variables DUAs for three coverage levels: 100%, 90%, and 80%. The results show that the test suites that cover 90% of the state variables DUAs are the most cost-effective.
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    Topology inference of Smart Fabric grids - a virtual coordinate based approach
    (Colorado State University. Libraries, 2020) Pendharkar, Gayatri Arun, author; Jayasumana, Anura P., advisor; Maciejewski, Anthony A., committee member; Malaiya, Yashwant K., committee member
    Driven by increasing potency and decreasing cost/size of the electronic devices capable of sensing, actuating, processing and wirelessly communicating, the Internet of Things (IoT) is expanding into manufacturing plants, complex structures, and harsh environments with the potential to impact the way we live and work. Subnets of simple devices ranging from smart RFIDs to tiny sensors/actuators deployed in massive numbers forming complex 2-D surfaces, manifolds and complex 3-D physical spaces and fabrics will be a key constituent of this infrastructure. Smart Fabrics (SFs) are emerging with embedded IoT devices that have the ability to do things that traditional fabrics cannot, including sensing, storing, communicating, transforming data, and harvesting and conducting energy. These SFs are expected to have a wide range of applications in the near future in health monitoring, space stations, commercial building rooftops and more. With this innovative Smart Fabric technology at hand, there is a need to create algorithms for programming the smart nodes to facilitate communication, monitoring, and data routing within the fabric. Automatically detecting the location, shape, and other such physical characteristics will be essential but without resorting to localization techniques such as Global Positioning System (GPS), the size and cost of which may not be acceptable for many large-scale applications. Measuring the physical distances and obtaining geographical coordinates becomes infeasible for many IoT networks, particularly those deployed in harsh and complex environments. In SFs, the proximity between the nodes makes it impossible to deploy technology like GPS or Received Signal Strength Indicator (RSSI) for distance estimation. This thesis devises a Virtual Coordinate (VC) based method to identify the node positions and infer the shape of SFs with embedded grids of IoT devices. In various applications, we expect the nodes to communicate through randomly shaped fabrics in the presence of oddly-shaped holes. The geometry of node placement, the shape of the fabric, and dimensionality affect the identification, shape determination, and routing algorithms. The objective of this research is to infer the shape of fabric, holes, and other non-operational parts of the fabric with different grid placements. With the ability to construct the topology, efficient data routing can be achieved, damaged regions of fabric could be identified, and in general, the shape could be inferred for SFs with a wide range of sizes. Clothing and health monitoring being two essential segments of living, SFs that combines both would be a success in the textile market. SFs can be synthesized in space stations as compact sensing devices, assist in patient health monitoring, and also bring a spark to the showbiz. Identifying the position of different nodes/devices within SF grids is essential for applications and networking functions. We study and devise strategic methods for localization of SFs with rectangular grid placement of nodes using the VC approach, a viable alternative to geographical coordinates. In our system, VCs are computed using the hop distances to the anchors. For a full grid (no missing nodes), each grid node has predictable unique VCs. However, a SF grid may have holes/voids/obstacles that cause perturbations and distortion in VC pattern and may even result in non-unique VCs. Our shape inference method adaptively selects anchors from already localized nodes to compute VCs with the least amount of perturbation. We evaluate the proposed algorithm to simulate SF grids with varied sizes (i.e. number of nodes) and the number of voids. For each scenario, e.g. a SF grid with length X breadth dimensions - 19X19, 10% missing nodes, and 3 voids, we generate 60 samples of the grid with random possible placements and sizes of voids. Then, the localization algorithm is executed on these grids for all different scenarios. The final results measure the percentages of localized nodes as well as the total number of elected anchors required for the localization. We also investigate SF grids with triangular node placement and localization methods for the same. Additionally, parallelization techniques are implemented using an Message Parsing Interface (MPI) mechanism to run the simulations for rectangular and triangular grid SFs with efficient use of time and resources. To summarize, an algorithm was presented for the detection of voids in smart fabrics with embedded sensor nodes. It identifies the minimum set of node perturbations to be consistent with VCs and adaptively selects anchors to reduce uncertainty.
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    Unbiased phishing detection using domain name based features
    (Colorado State University. Libraries, 2018) Shirazi, Hossein, author; Ray, Indrakshi, advisor; Malaiya, Yashwant K., committee member; Vijayasarathy, Leo R., committee member
    Internet users are coming under a barrage of phishing attacks of increasing frequency and sophistication. While these attacks have been remarkably resilient against the vast range of defenses proposed by academia, industry, and research organizations, machine learning approaches appear to be a promising one in distinguishing between phishing and legitimate websites. There are three main concerns with existing machine learning approaches for phishing detection. The first concern is there is neither a framework, preferably open-source, for extracting feature and keeping the dataset updated nor an updated dataset of phishing and legitimate website. The second concern is the large number of features used and the lack of validating arguments for the choice of the features selected to train the machine learning classifier. The last concern relates to the type of datasets used in the literature that seems to be inadvertently biased with respect to the features based on URL or content. In this thesis, we describe the implementation of our open-source and extensible framework to extract features and create up-to-date phishing dataset. With having this framework, named Fresh-Phish, we implemented 29 different features that we used to detect whether a given website is legitimate or phishing. We used 26 features that were reported in related work and added 3 new features and created a dataset of 6,000 websites with these features of which 3,000 were malicious and 3,000 were genuine and tested our approach. Using 6 different classifiers we achieved the accuracy of 93% which is a reasonable high in this field. To address the second and third concerns, we put forward the intuition that the domain name of phishing websites is the tell-tale sign of phishing and holds the key to successful phishing detection. We focus on this aspect of phishing websites and design features that explore the relationship of the domain name to the key elements of the website. Our work differs from existing state-of-the-art as our feature set ensures that there is minimal or no bias with respect to a dataset. Our learning model trains with only seven features and achieves a true positive rate of 98% and a classification accuracy of 97%, on sample dataset. Compared to the state-of-the-art work, our per data instance processing and classification is 4 times faster for legitimate websites and 10 times faster for phishing websites. Importantly, we demonstrate the shortcomings of using features based on URLs as they are likely to be biased towards dataset collection and usage. We show the robustness of our learning algorithm by testing our classifiers on unknown live phishing URLs and achieve a higher detection accuracy of 99.7% compared to the earlier known best result of 95% detection rate.
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    Using slicing techniques to support scalable rigorous analysis of class models
    (Colorado State University. Libraries, 2015) Sun, Wuliang, author; Ray, Indrakshi, advisor; Bieman, James M., committee member; Malaiya, Yashwant K., committee member; Cooley, Daniel S., committee member
    Slicing is a reduction technique that has been applied to class models to support model comprehension, analysis, and other modeling activities. In particular, slicing techniques can be used to produce class model fragments that include only those elements needed to analyze semantic properties of interest. However, many of the existing class model slicing techniques do not take constraints (invariants and operation contracts) expressed in auxiliary constraint languages into consideration when producing model slices. Their applicability is thus limited to situations in which the determination of slices does not require information found in constraints. In this dissertation we describe our work on class model slicing techniques that take into consideration constraints expressed in the Object Constraint Language (OCL). The slicing techniques described in the dissertation can be used to produce model fragments that each consists of only the model elements needed to analyze specified properties. The slicing techniques are intended to enhance the scalability of class model analysis that involves (1) checking conformance between an object configuration and a class model with specified invariants and (2) analyzing sequences of operation invocations to uncover invariant violations. The slicing techniques are used to produce model fragments that can be analyzed separately. An evaluation we performed provides evidence that the proposed slicing techniques can significantly reduce the time to perform the analysis.
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    Virtual coordinate based techniques for wireless sensor networks: a simulation tool and localization & planarization algorithms
    (Colorado State University. Libraries, 2013) Shah, Pritam, author; Jayasumana, Anura P., advisor; Pasricha, Sudeep, committee member; Malaiya, Yashwant K., committee member
    Wireless sensor Networks (WSNs) are deployments of smart sensor devices for monitoring environmental or physical phenomena. These sensors have the ability to communicate with other sensors within communication range or with a base station. Each sensor, at a minimum, comprises of sensing, processing, transmission, and power units. This thesis focuses on virtual coordinate based techniques in WSNs. Virtual Coordinates (VCs) characterize each node in a network with the minimum hop distances to a set of anchor nodes, as its coordinates. It provides a compelling alternative to some of the localization applications such as routing. Building a WSN testbed is often infeasible and costly. Running real experiments on WSNs testbeds is time consuming, difficult and sometimes not feasible given the scope and size of applications. Simulation is, therefore, the most common approach for developing and testing new protocols and techniques for sensor networks. Though many general and wireless sensor network specific simulation tools are available, no available tool currently provides an intuitive interface or a tool for virtual coordinate based simulations. A simulator called VCSIM is presented which focuses specifically on Virtual Coordinate Space (VCS) in WSNs. With this simulator, a user can easily create WSNs networks of different sizes, shapes, and distributions. Its graphical user interface (GUI) facilitates placement of anchors and generation of VCs. Localization in WSNs is important for several reasons including identification and correlation of gathered data, node addressing, evaluation of nodes' density and coverage, geographic routing, object tracking, and other geographic algorithms. But due to many constraints, such as limited battery power, processing capabilities, hardware costs, and measurement errors, localization still remains a hard problem in WSNs. In certain applications, such as security sensors for intrusion detection, agriculture, land monitoring, and fire alarm sensors in a building, the sensor nodes are always deployed in an orderly fashion, in contrast to random deployments. In this thesis, a novel transformation is presented to obtain position of nodes from VCs in rectangular, hexagonal and triangular grid topologies. It is shown that with certain specific anchor placements, a location of a node can be accurately approximated, if the length of a shortest path in given topology between a node and anchors is equal to length of a shortest path in full topology (i.e. a topology without any voids) between the same node and anchors. These positions are obtained without the need of any extra localization hardware. The results show that more than 90% nodes were able to identify their position in randomly deployed networks of 80% and 85% node density. These positions can then be used for deterministic routing which seems to have better avg. path length compared to geographic routing scheme called "Greedy Perimeter Stateless Routing (GPSR)". In many real world applications, manual deployment is not possible in exact regular rectangular, triangular or hexagonal grids. Due to placement constraint, nodes are often placed with some deviation from ideal grid positions. Because of placement tolerance and due to non-isotropic radio patterns nodes may communicate with more or less number of neighbors than needed and may form cross-links causing non-planar topologies. Extracting planar graph from network topologies is known as network planarization. Network planarization has been an important technique in numerous sensor network protocols--such as GPSR for efficient routing, topology discovery, localization and data-centric storage. Most of the present planarization algorithms are based on location information. In this thesis, a novel network planarization algorithm is presented for rectangular, hexagonal and triangular topologies which do not use location information. The results presented in this thesis show that with placement errors of up to 30%, 45%, and 30% in rectangular, triangular and hexagonal topologies respectively we can obtain good planar topologies without the need of location information. It is also shown that with obtained planar topology more nodes acquire unique VCs.