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Browsing by Author "Malaiya, Yashwant, committee member"

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    A scenario-based technique to analyze UML design class models
    (Colorado State University. Libraries, 2014) Yu, Lijun, author; France, Robert B., advisor; Ray, Indrakshi, committee member; Ghosh, Sudipto, committee member; Malaiya, Yashwant, committee member; Turk, Dan, committee member
    Identifying and resolving design problems in the early design phases can help reduce the number of design errors in implementations. In this dissertation a tool-supported lightweight static analysis technique is proposed to rigorously analyze UML design class models that include operations specified using the Object Constraint Language (OCL). A UML design class model is analyzed against a given set of scenarios that describe desired or undesired behaviors. The technique can leverage existing class model analysis tools such as USE and OCLE. The analysis technique is lightweight in that it analyzes functionality specified in a UML design class model within the scope of a given set of scenarios. It is static because it does not require that the UML design class model be executable. The technique is used to (1) transform a UML design class model to a snapshot transition model that captures valid state transitions, (2) transform given scenarios to snapshot transitions and (3) determine if the snapshot transitions conform or not to the snapshot transition model. A design inconsistency exists if snapshot transitions that represent desired behaviors do not conform to the snapshot transition model, or if snapshot transitions representing undesired behaviors conform to the snapshot transition model. A Scenario-based UML Design Analysis tool was developed using Kermeta and the Eclipse Modeling Framework. The tool can be used to transform an Ecore design class model to a snapshot transition model and transform scenarios to snapshot transitions. The tool is integrated with the USE analysis tool. We used the Scenario-based UML Design Analysis technique to analyze two design class models: a Train Management System model and a Generalized Spatio-Temporal RBAC model. The two demonstration case studies show how the technique can be used to analyze the inconsistencies between UML design class models and scenarios. We performed a pilot study to evaluate the effectiveness of the Scenario-based UML Design Analysis technique. In the pilot study the technique uncovered at least as many design inconsistencies as manual inspection techniques uncovered, and the technique did not uncover false inconsistencies. The pilot study provides some evidence that the Scenario-based UML Design Analysis technique is effective. The dissertation also proposes two scenario generation techniques. These techniques can be used to ease the manual effort needed to produce scenarios. The scenario generation techniques can be used to automatically generate a family of scenarios that conform to specified scenario generation criteria.
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    An analysis of Internet of Things (IOT) ecosystem from the perspective of device functionality, application security and application accessibility
    (Colorado State University. Libraries, 2022) Paudel, Upakar, author; Ray, Indrakshi, advisor; Malaiya, Yashwant, committee member; Simske, Steve, committee member
    Internet of Thing (IoT) devices are being widely used in smart homes and organizations. IoT devices can have security vulnerabilities in different fronts: Device front with embedded functionalities and Application front. This work aims to analyze IoT devices security health from device functionality perspective and application security and accessibility perspective to understand holistic picture of entire IoT ecosystem's security health. An IoT device has some intended purposes, but may also have hidden functionalities. Typically, the device is installed in a home or an organization and the network traffic associated with the device is captured and analyzed to infer high-level functionality to the extent possible. However, such analysis is dynamic in nature, and requires the installation of the device and access to network data which is often hard to get for privacy and confidentiality reasons. In this work, we propose an alternative static approach which can infer the functionality of a device from vendor materials using Natural Language Processing (NLP) techniques. Information about IoT device functionality can be used in various applications, one of which is ensuring security in a smart home. We can also use the device functionalities in various security applications especially access control policies. Based on the functionality of a device we can provide assurance to the consumer that these devices will be compliant to the home or organizational policy even before they have been purchased. Most IoT devices interface with the user through mobile companion apps. Such apps are used to configure, update, and control the device(s) constituting a critical component in the IoT ecosystem, but they have historically been under-studied. In this thesis, we also perform security and accessibility analysis of IoT application on 265 apps to understand security and accessibility vulnerabilities present in the apps and identify some mitigating strategies.
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    Automated extraction of access control policy from natural language documents
    (Colorado State University. Libraries, 2023) Alqurashi, Saja, author; Ray, Indrakshi, advisor; Ray, Indrajit, committee member; Malaiya, Yashwant, committee member; Simske, Steve, committee member
    Data security and privacy are fundamental requirements in information systems. The first step to providing data security and privacy for organizations is defining access control policies (ACPs). Security requirements are often expressed in natural languages, and ACPs are embedded in the security requirements. However, ACPs in natural language are unstructured and ambiguous, so manually extracting ACPs from security requirements and translating them into enforceable policies is tedious, complex, expensive, labor-intensive, and error-prone. Thus, the automated ACPs specification process is crucial. In this thesis, we consider the Next Generation Access Control (NGAC) model as our reference formal access control model to study the automation process. This thesis addresses the research question: How do we automatically translate access control policies (ACPs) from natural language expression to the NGAC formal specification? Answering this research question entails building an automated extraction framework. The pro- posed framework aims to translate natural language ACPs into NGAC specifications automatically. The primary contributions of this research are developing models to construct ACPs in NGAC specification from natural language automatically and generating a realistic synthetic dataset of access control policies sentences to evaluate the proposed framework. Our experimental results are promising as we achieved, on average, an F1-score of 93 % when identifying ACPs sentences, an F1-score of 96 % when extracting NGAC relations between attributes, and an F1-score of 96% when extracting user attribute and 89% for object attribute from natural language access control policies.
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    Cooperative defense mechanisms for detection, identification and filtering of DDoS attacks
    (Colorado State University. Libraries, 2016) Mosharraf Ghahfarokhi, Negar, author; Jayasumana, Anura P., advisor; Ray, Indrakshi, advisor; Pezeshki, Ali, committee member; Malaiya, Yashwant, committee member
    To view the abstract, please see the full text of the document.
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    Coordinate repair and medial axis detection in virtual coordinate based sensor networks
    (Colorado State University. Libraries, 2014) Mahindre, Gunjan S., author; Jayasumana, Anura, advisor; Luo, J. Rockey, committee member; Malaiya, Yashwant, committee member
    Wireless Sensor Networks (WSNs) perform several operations like routing, topology extraction, data storage and data processing that depend on the efficiency of the localization scheme deployed in the network. Thus, WSNs need to be equipped with a good localization scheme as the addressing scheme affects the performance of the system as a whole. There are geographical as well as Virtual Coordinate Systems (VCS) for WSN localization. Although Virtual Coordinate (VC) based algorithms work well after system establishment, they are hampered by events such as node failure and link failure which are unpredictable and inevitable in WSNs where sensor nodes can have only a limited amount of energy to be used. This degrades the performance of algorithms and reduces the overall life of the network. WSNs, today, need a method to recover from such node failures at its foundation level and maintain its performance of various functions despite node failure events. The main focus of this thesis is preserving performance of virtual coordinate based algorithms in the presence of node failure. WSNs are subject to changes even during their operation. This implies that topology of the sensor networks can change dynamically throughout its life time. Knowing the shape, size and variations in the network topology helps to repair the algorithm better. Being centrally located in the network, medial nodes of a network provides us with information such as width of the network at a particular cross-section and distance of network nodes from boundary nodes. This information can be used as a foundation for applications such as network segmentation, VC system implementation, routing scheme implementation, topology extraction and efficient data storage and recovery. We propose a new approach for medial axis extraction in sensor networks. This distributed algorithm is very flexible with respect to the network shape and size. The main advantage of the algorithm is that, unlike existing algorithms, it works for networks with low node degrees. An algorithm for repairing VCS when network nodes fail is presented that eliminates the need for VC regeneration. This helps maintain efficient performance for all network sizes. The system performance degrades at higher node failure percentages with respect to the network size but the degradation is not abrupt and the system maintains a graceful degradation despite sudden node failure patterns. A hierarchical virtual coordinate system is proposed and evaluated for its response to network events like routing and node failures. We were also able to extract medial axis for various networks with the presented medial axis detection scheme. The networks used for testing fall under a range of shapes and an average node degree from 3 to 8. Discussions over the VC repair algorithm and the novel medial axis extraction scheme provide an insight into the nature of proposed schemes. We evaluate the scope and limitations for VCS repair algorithm and medial axis detection scheme. Performance of the VC repair algorithm in a WSN is evaluated over various conditions simulated to represent a practical node failure events to gauge the system response through routing percentage and average hop count over the network. We compare the results obtained through our medial axis detection scheme with existing state-of-the-art algorithm. The results show that this scheme overcomes the shortcomings of the medial axis detection schemes. The proposed medial axis detection technique enables us to extract the information held by a medial axis of a sensor network. The VC repair algorithm and the new medial axis extraction scheme perform very efficiently to make a WSN tolerant of node failure events.
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    CPS security testbed: requirement analysis, prototype design and protection framework
    (Colorado State University. Libraries, 2023) Talukder, Md Rakibul Hasan, author; Ray, Indrajit, advisor; Malaiya, Yashwant, committee member; Vijayasarathy, Leo, committee member
    Testbeds are a practical way to perform security exercises on cyber physical systems (CPS) to understand vulnerabilities and the progression/impact of cyber-attacks. However, it is challenging to replicate a large CPS, such as nuclear power plant or an electrical power grid, within the confines of a laboratory that would allow security experiments to be carried out. Thus, software-based simulations are getting increasingly popular as opposed to hardware-in-the-loop based simulations for CPS that form a critical infrastructure. Unfortunately, a software-based CPS testbed oriented towards security-centric experiments requires a careful re-examination of requirements and architectural design different from a CPS testbed for non-security related experiments. On a security-focused testbed there is a need to run real attack scripts for red-teaming/blue-teaming exercises, which are, in the strictest sense of the term, malicious in nature. Thus, there is a need to protect the testbed itself from these attack experiments that have the potential to go awry. The overall effect of an exploit on the whole system or vulnerabilities at communication channels needs to be particularly explored while building a simulator for a security-centric CPS. Besides, when multiple experiments are conducted on the same testbed, there is a need to maintain isolation among these experiments so that no experiment can accidentally or maliciously compromise others and affect the fidelity of those results. Specific security experiment-related supports are essential when designing such a testbed but integrating a software-based simulator within the testbed to provide necessary experiment support is challenging. In this thesis, we make three contributions. First, we present the design of an ideal testbed based on a set of requirements and supports that we have identified, focusing specifically on security experiment as the primary use case. Next, following these requirements analysis, we integrate a software-based simulator (Generic Pressurized Water Reactor) into a testbed design by modifying the implementation architecture to allow the execution of attack experiments on different networking architectures and protocols. Finally, we describe a novel security architecture and framework to ensure the protection of security-related experiments on a CPS testbed.
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    Design methodology and productivity improvement in high speed VLSI circuits
    (Colorado State University. Libraries, 2017) Hossain, KM Mozammel, author; Chen, Thomas W., advisor; Malaiya, Yashwant, committee member; Pasricha, Sudeep, committee member; Pezeshki, Ali, committee member
    To view the abstract, please see the full text of the document.
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    On component-oriented access control in lightweight virtualized server environments
    (Colorado State University. Libraries, 2017) Belyaev, Kirill, author; Ray, Indrakshi, advisor; Ray, Indrajit, committee member; Malaiya, Yashwant, committee member; Vijayasarathy, Leo, committee member
    With the advancements in contemporary multi-core CPU architectures and increase in main memory capacity, it is now possible for a server operating system (OS), such as Linux, to handle a large number of concurrent services on a single server instance. Individual components of such services may run in different isolated runtime environments, such as chrooted jails or related forms of OS-level containers, and may need restricted access to system resources and the ability to share data and coordinate with each other in a regulated and secure manner. In this dissertation we describe our work on the access control framework for policy formulation, management, and enforcement that allows access to OS resources and also permits controlled data sharing and coordination for service components running in disjoint containerized environments within a single Linux OS server instance. The framework consists of two models and the policy formulation is based on the concept of policy classes for ease of administration and enforcement. The policy classes are managed and enforced through a Lightweight Policy Machine for Linux (LPM) that acts as the centralized reference monitor and provides a uniform interface for regulating access to system resources and requesting data and control objects. We present the details of our framework and also discuss the preliminary implementation and evaluation to demonstrate the feasibility of our approach.
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    Optimal design space exploration for FPGA-based accelerators: a case study on 1-D FDTD
    (Colorado State University. Libraries, 2015) Puranik, Mugdha, author; Rajopadhye, Sanjay, advisor; Pasricha, Sudeep, committee member; Malaiya, Yashwant, committee member
    Hardware accelerators are optimized functional blocks designed to offload specific tasks from the CPU, speed up them up and reduce their dynamic power consumption. It is important to develop a methodology to efficiently implement critical algorithms on the hardware accelerator and do systematic design space exploration to identify optimal designs. In this thesis, we design, as a case study, a hardware accelerator for the 1-D Finite Difference Time Domain (FDTD) algorithm, a compute intensive technique for modeling electromagnetic behavior. Memory limitations and bandwidth constraints result in long run times on large problems. Hence, an approach which increases the speed of the FDTD method and reduces bandwidth requirement is necessary. To achieve this, we design an FPGA based hardware accelerator. We implement the accelerator based on time-space tiling. In our design, p processing elements (PEs) execute p parallelogram shaped tiles in parallel, each of which constitutes one tile pass. Our design uses a small amount of redundant computation to enable all PEs to start "nearly" concurrently, thereby fully exploiting the available parallelism. A further optimization allows us to reduce the main memory data transfers of this design by a factor of two. These optimizations are integrated in hardware, and implemented in Verilog in Altera's Quartus II, yielding a PE that delivers a throughput of one "iteration (i.e., two results) per cycle". To explore the feasible design space systematically, we formulate an optimization problem with the objective of minimizing the total execution time for given resource constraints. We solve the optimization problem analytically, and therefore have a provably optimal design in the feasible space. We also observe that for different problem sizes reveal that the optimal design may not always match the common sense intuition.
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    Privacy preserving linkage and sharing of sensitive data
    (Colorado State University. Libraries, 2018) Lazrig, Ibrahim Meftah, author; Ray, Indrakshi, advisor; Ray, Indrajit, advisor; Malaiya, Yashwant, committee member; Vijayasarathy, Leo, committee member; Ong, Toan, committee member
    Sensitive data, such as personal and business information, is collected by many service providers nowadays. This data is considered as a rich source of information for research purposes that could benet individuals, researchers and service providers. However, because of the sensitivity of such data, privacy concerns, legislations, and con ict of interests, data holders are reluctant to share their data with others. Data holders typically lter out or obliterate privacy related sensitive information from their data before sharing it, which limits the utility of this data and aects the accuracy of research. Such practice will protect individuals' privacy; however it prevents researchers from linking records belonging to the same individual across dierent sources. This is commonly referred to as record linkage problem by the healthcare industry. In this dissertation, our main focus is on designing and implementing ecient privacy preserving methods that will encourage sensitive information sources to share their data with researchers without compromising the privacy of the clients or aecting the quality of the research data. The proposed solution should be scalable and ecient for real-world deploy- ments and provide good privacy assurance. While this problem has been investigated before, most of the proposed solutions were either considered as partial solutions, not accurate, or impractical, and therefore subject to further improvements. We have identied several issues and limitations in the state of the art solutions and provided a number of contributions that improve upon existing solutions. Our rst contribution is the design of privacy preserving record linkage protocol using semi-trusted third party. The protocol allows a set of data publishers (data holders) who compete with each other, to share sensitive information with subscribers (researchers) while preserving the privacy of their clients and without sharing encryption keys. Our second contribution is the design and implementation of a probabilistic privacy preserving record linkage protocol, that accommodates discrepancies and errors in the data such as typos. This work builds upon the previous work by linking the records that are similar, where the similarity range is formally dened. Our third contribution is a protocol that performs information integration and sharing without third party services. We use garbled circuits secure computation to design and build a system to perform the record linkages between two parties without sharing their data. Our design uses Bloom lters as inputs to the garbled circuits and performs a probabilistic record linkage using the Dice coecient similarity measure. As garbled circuits are known for their expensive computations, we propose new approaches that reduce the computation overhead needed, to achieve a given level of privacy. We built a scalable record linkage system using garbled circuits, that could be deployed in a distributed computation environment like the cloud, and evaluated its security and performance. One of the performance issues for linking large datasets is the amount of secure computation to compare every pair of records across the linked datasets to nd all possible record matches. To reduce the amount of computations a method, known as blocking, is used to lter out as much as possible of the record pairs that will not match, and limit the comparison to a subset of the record pairs (called can- didate pairs) that possibly match. Most of the current blocking methods either require the parties to share blocking keys (called blocks identiers), extracted from the domain of some record attributes (termed blocking variables), or share reference data points to group their records around these points using some similarity measures. Though these methods reduce the computation substantially, they leak too much information about the records within each block. Toward this end, we proposed a novel privacy preserving approximate blocking scheme that allows parties to generate the list of candidate pairs with high accuracy, while protecting the privacy of the records in each block. Our scheme is congurable such that the level of performance and accuracy could be achieved according to the required level of privacy. We analyzed the accuracy and privacy of our scheme, implemented a prototype of the scheme, and experimentally evaluated its accuracy and performance against dierent levels of privacy.
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    Silicon photonic hardware accelerators for transformers and graph neural networks
    (Colorado State University. Libraries, 2023) Afifi, Salma, author; Pasricha, Sudeep, advisor; Nikdast, Mahdi, committee member; Malaiya, Yashwant, committee member
    The rapid growth of artificial intelligence (AI) applications has revolutionized the way we process data, make decisions, and interact with machines. Specifically, artificial neural networks (ANNs) have significantly evolved and now encompass various advanced neural networks such as transformers and graph neural networks (GNNs). This has enabled the development of innovative AI applications that can transform several industries, including healthcare, recommendation systems, and robotics. Transformer and transformer-based neural networks have outperformed multiple ANNs, such as convolution neural networks (CNNs) and recurrent neural networks (RNNs), across many natural language processing (NLP) tasks. Moreover, transformers are currently being integrated into vision tasks through using the vision transformer model (ViT). Similarly, GNNs have witnessed a surge of advancements over the past few years and have established their proficiency in dealing with graph-structured data. Nevertheless, each of these neural networks imposes unique challenges, hindering their inference and usage in resource-constrained systems. For instance, the transformer model's size, number of parameters, and complexity of operations lead to long inference times, large memory footprint, and low computation-to-memory ratio. On the other hand, GNNs inference challenges are due to their dense and very sparse computations. Additionally, the wide variety of possible input graphs structure and algorithms dictate the need for a system capable of efficiently adapting their execution and operations to the specific graph structure and effectively scaling to extremely large graphs. Accordingly, conventional computing processors and ANN accelerators are not tailored to cater for such challenges, and using them to accelerate transformers and GNN execution can be highly inefficient. ii Furthermore, the utilization of traditional electronic accelerators entails a number of limitations, including escalating fabrication costs due to low yields and diminishing performance improvements, associated with semiconductor-technology scaling. This has led researchers to start investigating other technologies for ANN acceleration such as silicon photonics which enables performing complex operations in the optical domain with low energy consumption and at very high throughput. While several hardware accelerators leveraging silicon photonics have been presented for networks such as CNNs, none have been customized for emerging complex neural networks such as transformers and GNNs. Due to the various challenges associated with each of these networks, designing reliable and efficient inference hardware accelerators for transformers and GNNs is a non-trivial problem. This thesis introduces two novel silicon-photonic-based hardware architectures for energy efficient and high throughput inference acceleration. As our first contribution, we propose a non-coherent silicon photonic hardware accelerator for transformer neural networks, called TRON. We demonstrate how TRON is able to accommodate a wide range of transformer and transformer-based neural networks while surpassing GPU, CPU, TPU, and several state-of-the-art transformer hardware accelerators. For GNN inference acceleration, we propose GHOST, a hardware accelerator that integrates various device-, circuit- and architecture-level optimizations which enable it to efficiently process a broad family of GNNs and real-world graph structures and sizes. When compared to multiple state-of-the-art GNN hardware accelerators, GPUs, CPUs, and TPUs, our experiments showcase how GHOST exhibits significantly better performance and energy efficiency.
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    Throughput optimization techniques for heterogeneous architectures
    (Colorado State University. Libraries, 2024) Derumigny, Nicolas, author; Pouchet, Louis-Noël, advisor; Rastello, Fabrice, advisor; Hack, Sebastian, committee member; Rohou, Erven, committee member; Malaiya, Yashwant, committee member; Ortega, Francisco, committee member; Pétrot, Frédéric, committee member; Wilson, James, committee member; Zaks, Ayal, committee member
    Moore's Law has allowed during the past 40 years to exponentially increase transistor density of integrated circuits. As a result, computing devices ranging from general-purpose processors to dedicated accelerators have become more and more complex due to the specialization and the multiplication of their compute units. Therefore, both low-level program optimization (e.g. assembly-level programming and generation) and accelerator design must solve the issue of efficiently mapping the input program computations to the various chip capabilities. However, real-world chip blueprints are not openly accessible in practice, and their documentation is often incomplete. Given the diversity of CPUs available (Intel's / AMD's / Arm's microarchitectures), we tackle in this manuscript the problem of automatically inferring a performance model applicable to fine-grain throughput optimization of regular programs. Furthermore, when order of magnitude of performance gain over generic accelerators are needed, domain-specific accelerators must be considered; which raises the same question of the number of dedicated units as well as their functionality. To remedy this issue, we present two complementary approaches: on one hand, the study of single-application specialized accelerators with an emphasis on hardware reuse, and, on the other hand, the generation of semi-specialized designs suited for a user-defined set of applications.
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    Time-delta method for measuring software development contribution rates
    (Colorado State University. Libraries, 2024) Bishop, Vincil Chapman, III, author; Simske, Steven J., advisor; Vans, Marie, committee member; Malaiya, Yashwant, committee member; Ray, Indrajit, committee member
    The Time-Delta Method for estimating software development contribution rates provides insight into the efficiency and effectiveness of software developers. It proposes and evaluates a framework for assessing software development contribution and its rate (first derivative) based on Commit Time Delta (CTD) and software complexity metrics. The methodology relies on analyzing historical data from software repositories, employing statistical techniques to infer developer productivity and work patterns. The approach combines existing metrics like Cyclomatic Complexity with novel imputation techniques to estimate unobserved work durations, offering a practical tool for evaluating the engagement of software developers in a production setting. The findings suggest that this method can serve as a reliable estimator of development effort, with potential implications for optimizing software project management and resource allocation.
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    Toward robust embedded networks in heavy vehicles - machine learning strategies for fault tolerance
    (Colorado State University. Libraries, 2024) Ghatak, Chandrima, author; Ray, Indrakshi, advisor; Malaiya, Yashwant, committee member; Kokoszka, Piotr, committee member
    In the domain of critical infrastructure, Medium and Heavy Duty (MHD) vehicles play an integral role in both military and civilian operations. These vehicles are essential for the efficiency and reliability of modern logistics. The operations of modern MHD vehicles are heavily automated through embedded computers called Electronic Control Units (ECUs). These ECUs utilize arrays of sensors to control and optimize various vehicle functions and are critical to maintaining operational effectiveness. In most MHD vehicles, this sensor data is predominantly communicated using the Society of Automotive Engineering's (SAE) J1939 Protocol over Controller Area Networks (CAN) and is vital for the smooth functioning of MHD vehicles. The resilience of these communication networks is especially crucial in adversarial environments where sensor systems are susceptible to disruptions caused by physical (kinetic) or cyber-attacks. This dissertation presents an innovative approach using predictive machine learning algorithms to forecast accurate sensor readings in scenarios where sensor systems become compromised. The study focuses on the SAE J1939 networks in MHD vehicles, utilizing real-world data from a Class 6 Kenworth T270 truck. Three distinct machine-learning methods are explored and evaluated for their effectiveness in predicting missing sensor data. The results demonstrate that these models can nearly accurately predict sensor data, which is essential in preventing the vehicle from entering engine protection or limp modes, thereby extending operational capacity under adverse conditions. Overall, this research highlights the potential of machine learning in enhancing the resilience of networked cyber-physical systems, particularly in MHD vehicles. It underscores the significance of predictive algorithms in maintaining operational feasibility and contributes to the broader discussion on the resilience of critical infrastructure in hostile settings.
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    Towards automated security and privacy policies specification and analysis
    (Colorado State University. Libraries, 2024) Alqurashi, Saja Salem, author; Ray, Indrakshi, advisor; Ray, Indrajit, committee member; Malaiya, Yashwant, committee member; Simske, Steve, committee member
    Security and privacy policies, vital for information systems, are typically expressed in natural language documents. Security policy is represented by Access Control Policies (ACPs) within security requirements, initially drafted in natural language and subsequently translated into enforce- able policy. The unstructured and ambiguous nature of the natural language documents makes the manual translation process tedious, expensive, labor-intensive, and prone to errors. On the other hand, Privacy policy, with its length and complexity, presents unique challenges. The dense language and extensive content of the privacy policies can be overwhelming, hindering both novice users and experts from fully understanding the practices related to data collection and sharing. The disclosure of these data practices to users, as mandated by privacy regulations such as the General Data Protection Regulation (GDPR) and the California Consumer Privacy Act (CCPA), is of utmost importance. To address these challenges, we have turned to Natural Language Processing (NLP) to automate extracting critical information from natural language documents and analyze those security and privacy policies. Thus, this dissertation aims to address two primary research questions: Question 1: How can we automate the translation of Access Control Policies (ACPs) from natural language expressions to the formal model of Next Generation Access Control (NGAC) and subsequently analyze the generated model? Question 2: How can we automate the extraction and analysis of data practices from privacy policies to ensure alignment with privacy regulations (GDPR and CCPA)? Addressing these research questions necessitates the development of a comprehensive framework comprising two key components. The first component, SR2ACM, focuses on translating natural language ACPs into the NGAC model. This component introduces a series of innovative contributions to the analysis of security policies. At the core of our contributions is an automated approach to constructing ACPs within the NGAC specification directly from natural language documents. Our approach integrates machine learning with software testing, a novel methodology to ensure the quality of the extracted access control model. The second component, Privacy2Practice, is designed to automate the extraction and analysis of the data practices from privacy policies written in natural language. We have developed an automated method to extract data practices mandated by privacy regulations and to analyze the disclosure of these data practices within the privacy policies. The novelty of this research lies in creating a comprehensive framework that identifies the critical elements within security and privacy policies. Thus, this innovative framework enables automated extraction and analysis of both types of policies directly from natural language documents.